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Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
upcoming platforms, create platform definitions for those platforms.

Change-Id: Ic5df9fed02c44e65ec260bbb5efc1b8dbd919a56
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.

Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.

Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

* changes:
  zynqmp: pm: Update flags in common clk divisor node
  zynqmp: pm_api_clock: Copy only the valid bytes

The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.

The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
 Consider a case of nand_ref clock which has 2 divisor and 1 mux.
 The frequency of mux clock is 1500MHz and default value of div1 and
 div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
 When driver requests 80MHz for nand_ref clock, clock framework will
 adjust the div2 value to 1 (setting div2 value 2 results final clock
 to 50MHz which is more inaccurate compare to 100Mhz) which results
 final clock to 100MHz.
 Ideally the value of div1 and div2 should be updated to 19 and 1
 respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58

This patches copies only the valid part of string and
avoids filling junk at the end.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7

* changes:
  mediatek: mt8192: dcm: Add mcusys related dcm drivers
  mediatek: mt8192: add ptp3 driver
  mediatek: mt8192: Add SiP service
  mediatek: mt8192: add uart save and restore api
  mediatek: mt8192: modify sys_cirq driver
  mediatek: mt8192: add power-off support
  mediatek: mt8192: add pmic mt6359p driver
  mediatek: mt8192: Initialize delay_timer
  mediatek: mt8192: enable NS access for systimer
  mediatek: mt8192: Add CPU hotplug and MCDI support
  mediatek: mt8192: Add MCDI drivers
  mediatek: mt8192: Add SPMC driver

1. Add mcusys related dcm drivers
2. Turn on mcusys-related dcm by default

Change-Id: Ibbee37c87cc38e7a6cd7c93c2fc0817aad6dbe95
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

enable PTP3 for protecting sysPi
Signed-off-by: elly.chiang <elly.chiang@mediatek.com>
Change-Id: Ic3a13c8314f829dca8547861b98639d1d9444eb2

Add the basic SiP service

Change-Id: Ib7f2380aab910adf8d33498a79ecd287273907c5
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

When system resume, we want to print log as soon as possible.
So we add uart save and restore api, and they will be called
when systtem suspend and resume.

Change-Id: I83b477fd2b39567c9c6b70534ef186993f7053ae
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com>
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

1.Modify this driver to make it more complete and more standard.
2.And makes this driver available for more IC services.
3.Solve some bugs in the software.
Signed-off-by: G.Pangao <gtk_pangao@mediatek.com>
Change-Id: I284956d47ebbbd550ec93767679181185e442348

add power-off support
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: If19e99971515a8ae1ac9ae21046e4382adc18a69

add pmic mt6359p driver
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I20f2218f7d2087e8d2bf31258cf92a02e0dab77d

Init delay_timer for the use of delay functions

Change-Id: I35aefd7515bb9259634c8b6bc37d8c74da96e8f1
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

Enable NS access for all systimers.
Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a

Implement PSCI platform OPs to support CPU hotplug and MCDI.

Change-Id: I31abfc752b69ac40e70bc9e7a55163eb39776c44
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

Add MCDI related drivers to handle CPU powered on/off in CPU suspend.

Change-Id: I5110461e8eef86f8383b45f197ec5cb10dbfeb3e
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

Add SPMC driver for CPU power on/off.

Change-Id: I526b98d5885855efce019dd09cfd93b8816cbf19
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

* changes:
  plat: xilinx: zynqmp: Enable log messages for debug
  plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG

* changes:
  plat: marvell: armada: a3k: Simplify check if WTP variable is defined
  plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
  plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
  plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
  plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
  plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
  plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
  plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
  plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ieb352f0765882efdcb64ef54e6b2a39768590a06

These two targets are build by make subprocesses and are independent.
So splitting them into own targets allow make to build them in parallel.
$(TIMBUILD) script depends on $(TIMDDRTOOL) so specify it in Makefile.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I139fc7fe64d8de275b01a853e15bfb88c4ff840d

Add check when building mrvl_bootimage that size of bl1 image is not bigger
than maximal size.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib873debd3cfdba9acd4c168ee37edab3032e9f25

FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile target which specify
non-file targets and therefore needs to be always rebuilt.

Targets clean, realclean and distclean are .PHONY targets used to remove
built files. Correctly set that mrvl_clean target is prerequisite for these
clean targets to ensure that built files are removed.

Finally this change with usage of FORCE target allows to remove mrvl_clean
hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used
just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2fa8971244b43f101d846fc433ef7b0b6f139c92

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id766db4a900a56c795fe5ffdd8a2b80b1aaa2132

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaecd6c24bf334a959ac2bf395c3ee49c810b01a7

Create copy of WTMI images instead of moving them into TF-A build directory.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc24c33b9ce540e4acde51fc1a5c946ae66a5d7

Rather create a temporary copy in $(BUILD_PLAT) and modify only copy.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I256c029106ea6f69faa086fc4e5bee9f68cd257f

$(WTMI_IMG) is used only by $(MAKE) subprocess in $(DOIMAGEPATH) directory.
So calling truncate on $(WTMI_IMG) after $(MAKE) in $(DOIMAGEPATH) has no
effect and can just damage input file for future usage. Therefore remove
this truncate call.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9925c54c5d3d10eadc19825c5565ad4598a739a7

Save some space by enabling the log messages like bl33 address
only for debug builds. Also check the bl33 and bl32 address and
print only if this is not NULL.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I58d846bf69a75e839eb49abcbb9920af13296886

For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. So, change its name from PM_BOOT_HEALTH_STATUS_REG
to PMU_GLOBAL_GEN_STORAGE4.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I2f5c4c6a161121e7cdb4b9f0f8711d0dad16c372

Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done in the commit #1322dc94

.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8