1. 15 Sep, 2020 1 commit
  2. 10 Sep, 2020 1 commit
  3. 28 Aug, 2020 2 commits
  4. 18 Aug, 2020 2 commits
    • Manish V Badarkhe's avatar
      Add wrapper for AT instruction · 86ba5853
      Manish V Badarkhe authored
      
      
      In case of AT speculative workaround applied, page table walk
      is disabled for lower ELs (EL1 and EL0) in EL3.
      Hence added a wrapper function which temporarily enables page
      table walk to execute AT instruction for lower ELs and then
      disables page table walk.
      
      Execute AT instructions directly for lower ELs (EL1 and EL0)
      assuming page table walk is enabled always when AT speculative
      workaround is not applied.
      
      Change-Id: I4ad4c0bcbb761448af257e9f72ae979473c0dde8
      Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      86ba5853
    • Manish V Badarkhe's avatar
      plat/arm: remove common code for soc-id feature · 7f03d80d
      Manish V Badarkhe authored
      
      
      Removed common code for soc-id feature which is applicable
      for all arm platforms.
      
      In subsequent patches, added a platform based functions
      for FVP and Juno to retrieve the soc-id information.
      
      Change-Id: Idb632a935758a6caff2ca03a6eab8f663da8a93a
      Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      7f03d80d
  5. 14 Aug, 2020 2 commits
    • Manish Pandey's avatar
      plat/arm: enable support for Plat owned SPs · 990d972f
      Manish Pandey authored
      
      
      For Arm platforms SPs are loaded by parsing tb_fw_config.dts and
      adding them to SP structure sequentially, which in-turn is appended to
      loadable image list.
      
      With recently introduced dualroot CoT for SPs where they are owned
      either by SiP or by Platform. SiP owned SPs index starts at SP_PKG1_ID
      and Plat owned SPs index starts at SP_PKG5_ID. As the start index of SP
      depends on the owner, there should be a mechanism to parse owner of a SP
      and put it at the correct index in SP structure.
      
      This patch adds support for parsing a new optional field "owner" and
      based on it put SP details(UUID & Load-address) at the correct index in
      SP structure.
      
      Change-Id: Ibd255b60d5c45023cc7fdb10971bef6626cb560b
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      990d972f
    • Jimmy Brisson's avatar
      Prevent colliding identifiers · d74c6b83
      Jimmy Brisson authored
      
      
      There was a collision between the name of the typedef in the CASSERT and
      something else, so we make the name of the typedef unique to the
      invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into
      the macro. This eliminates the following MISRA violation:
      
          bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier
          "invalid_svc_uuid" is already used to represent a typedef.
      
      This also resolves MISRA rule 5.9.
      
      These renamings are as follows:
        * tzram -> secram. This matches the function call name as it has
        sec_mem in it's  name
        * fw_config_base -> config_base. This file does not mess with
        hw_conig, so there's little chance of confusion
      
      Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e
      Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      d74c6b83
  6. 10 Aug, 2020 1 commit
    • Alexei Fedorov's avatar
      plat/arm: Reduce size of BL31 binary · fa1fdb22
      Alexei Fedorov authored
      
      
      BL31 binary size is aligned to 4KB because of the
      code in include\plat\arm\common\arm_reclaim_init.ld.S:
          __INIT_CODE_UNALIGNED__ = .;
          . = ALIGN(PAGE_SIZE);
          __INIT_CODE_END__ = .;
      with all the zero data after the last instruction of
      BL31 code to the end of the page.
      This causes increase in size of BL31 binary stored in FIP
      and its loading time by BL2.
      This patch reduces the size of BL31 image by moving
      page alignment from __INIT_CODE_END__ to __STACKS_END__
      which also increases the stack size for secondary CPUs.
      
      Change-Id: Ie2ec503fc774c22c12ec506d74fd3ef2b0b183a9
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      fa1fdb22
  7. 31 Jul, 2020 1 commit
    • Manish Pandey's avatar
      tbbr/dualroot: rename SP package certificate file · 03a5225c
      Manish Pandey authored
      
      
      Currently only single signing domain is supported for SP packages but
      there is plan to support dual signing domains if CoT is dualroot.
      
      SP_CONTENT_CERT_ID is the certificate file which is currently generated
      and signed with trusted world key which in-turn is derived from Silicon
      provider RoT key.
      To allow dual signing domain for SP packages, other certificate file
      will be derived from Platform owned RoT key.
      
      This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
      does other related changes.
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
      03a5225c
  8. 30 Jul, 2020 1 commit
  9. 26 Jul, 2020 1 commit
  10. 24 Jul, 2020 1 commit
  11. 23 Jul, 2020 4 commits
  12. 21 Jul, 2020 2 commits
  13. 29 Jun, 2020 1 commit
  14. 25 Jun, 2020 1 commit
    • Manish V Badarkhe's avatar
      plat/arm: Load and populate fw_config and tb_fw_config · 82869675
      Manish V Badarkhe authored
      
      
      Modified the code to do below changes:
      
      1. Load tb_fw_config along with fw_config by BL1.
      2. Populate fw_config device tree information in the
         BL1 to load tb_fw_config.
      3. In BL2, populate fw_config information to retrieve
         the address of tb_fw_config and then tb_fw_config
         gets populated using retrieved address.
      4. Avoid processing of configuration file in case of error
         value returned from "fw_config_load" function.
      5. Updated entrypoint information for BL2 image so
         that it's arg0 should point to fw_config address.
      Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      Change-Id: Ife6f7b673a074e7f544ee3d1bda7645fd5b2886c
      82869675
  15. 24 Jun, 2020 3 commits
  16. 09 Jun, 2020 2 commits
    • Madhukar Pappireddy's avatar
      plat/fvp: Add support for dynamic description of secure interrupts · 452d5e5e
      Madhukar Pappireddy authored
      
      
      Using the fconf framework, the Group 0 and Group 1 secure interrupt
      descriptors are moved to device tree and retrieved in runtime. This
      feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.
      
      Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
      Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      452d5e5e
    • Manish Pandey's avatar
      dualroot: add chain of trust for secure partitions · 44f1aa8e
      Manish Pandey authored
      
      
      A new certificate "sip-sp-cert" has been added for Silicon Provider(SiP)
      owned Secure Partitions(SP). A similar support for Platform owned SP can
      be added in future. The certificate is also protected against anti-
      rollback using the trusted Non-Volatile counter.
      
      To avoid deviating from TBBR spec, support for SP CoT is only provided
      in dualroot.
      Secure Partition content certificate is assigned image ID 31 and SP
      images follows after it.
      
      The CoT for secure partition look like below.
      +------------------+       +-------------------+
      | ROTPK/ROTPK Hash |------>| Trusted Key       |
      +------------------+       | Certificate       |
                                 | (Auth Image)      |
                                /+-------------------+
                               /                   |
                              /                    |
                             /                     |
                            /                      |
                           L                       v
      +------------------+       +-------------------+
      | Trusted World    |------>| SiP owned SPs     |
      | Public Key       |       | Content Cert      |
      +------------------+       | (Auth Image)      |
                              /   +-------------------+
                             /                      |
                            /                      v|
      +------------------+ L     +-------------------+
      | SP_PKG1 Hash     |------>| SP_PKG1           |
      |                  |       | (Data Image)      |
      +------------------+       +-------------------+
              .                           .
              .                           .
              .                           .
      +------------------+       +-------------------+
      | SP_PKG8 Hash     |------>| SP_PKG8           |
      |                  |       | (Data Image)      |
      +------------------+       +-------------------+
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      Change-Id: Ia31546bac1327a3e0b5d37e8b99c808442d5e53f
      44f1aa8e
  17. 27 May, 2020 1 commit
    • Manish V Badarkhe's avatar
      Fix the build error for dualroot chain of trust. · b58956e9
      Manish V Badarkhe authored
      
      
      Fixed build error for dualroot chain of trust.
      Build error were thrown as below while compiling the code for
      dualroot chain of trust:
      
      aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
      (.bss.auth_img_flags+0x0): multiple definition of `auth_img_flags';
      ./build/fvp/debug/bl1/cot.o:(.bss.auth_img_flags+0x0): first defined here
      
      aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
      (.rodata.cot_desc_size+0x0): multiple definition of `cot_desc_size';
      ./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_size+0x0): first defined here
      
      aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
      (.rodata.cot_desc_ptr+0x0): multiple definition of `cot_desc_ptr';
      ./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_ptr+0x0): first defined here
      Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      Change-Id: I1a426c4e7f5f8013d71dafc176c7467c1b329757
      b58956e9
  18. 21 May, 2020 1 commit
  19. 19 May, 2020 1 commit
  20. 15 May, 2020 1 commit
  21. 29 Apr, 2020 1 commit
    • Andre Przywara's avatar
      fdt/wrappers: Replace fdtw_read_cells() implementation · ff4e6c35
      Andre Przywara authored
      Our fdtw_read_cells() implementation goes to great lengths to
      sanity-check every parameter and result, but leaves a big hole open:
      The size of the storage the value pointer points at needs to match the
      number of cells given. This can't be easily checked at compile time,
      since we lose the size information by using a void pointer.
      Regardless the current usage of this function is somewhat wrong anyways,
      since we use it on single-element, fixed-length properties only, for
      which the DT binding specifies the size.
      Typically we use those functions dealing with a number of cells in DT
      context to deal with *dynamically* sized properties, which depend on
      other properties (#size-cells, #clock-cells, ...), to specify the number
      of cells needed.
      
      Another problem with the current implementation is the use of
      ambiguously sized types (uintptr_t, size_t) together with a certain
      expectation about their size. In general there is no relation between
      the length of a DT property and the bitness of the code that parses the
      DTB: AArch64 code could encounter 32-bit addresses (where the physical
      address space is limited to 4GB [1]), while AArch32 code could read
      64-bit sized properties (/memory nodes on LPAE systems, [2]).
      
      To make this more clear, fix the potential issues and also align more
      with other DT users (Linux and U-Boot), introduce functions to explicitly
      read uint32 and uint64 properties. As the other DT consumers, we do this
      based on the generic "read array" function.
      Convert all users to use either of those two new functions, and make
      sure we never use a pointer to anything other than uint32_t or uint64_t
      variables directly.
      
      This reveals (and fixes) a bug in plat_spmd_manifest.c, where we write
      4 bytes into a uint16_t variable (passed via a void pointer).
      
      Also we change the implementation of the function to better align with
      other libfdt users, by using the right types (fdt32_t) and common
      variable names (*prop, prop_names).
      
      [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi#n874
      [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/ecx-2000.dts
      
      
      
      Change-Id: I718de960515117ac7a3331a1b177d2ec224a3890
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      ff4e6c35
  22. 28 Apr, 2020 1 commit
    • Andre Przywara's avatar
      fdt/wrappers: Generalise fdtw_read_array() · 6e3a89f4
      Andre Przywara authored
      
      
      Currently our fdtw_read_array() implementation requires the length of
      the property to exactly match the requested size, which makes it less
      flexible for parsing generic device trees.
      Also the name is slightly misleading, since we treat the cells of the
      array as 32 bit unsigned integers, performing the endianess conversion.
      
      To fix those issues and align the code more with other DT users (Linux
      kernel or U-Boot), rename the function to "fdt_read_uint32_array", and
      relax the length check to only check if the property covers at least the
      number of cells we request.
      This also changes the variable names to be more in-line with other DT
      users, and switches to the proper data types.
      
      This makes this function more useful in later patches.
      
      Change-Id: Id86f4f588ffcb5106d4476763ecdfe35a735fa6c
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      6e3a89f4
  23. 02 Apr, 2020 1 commit
  24. 25 Mar, 2020 1 commit
  25. 23 Mar, 2020 1 commit
  26. 17 Mar, 2020 1 commit
  27. 16 Mar, 2020 1 commit
    • Louis Mayencourt's avatar
      fconf: Clean Arm IO · a6de824f
      Louis Mayencourt authored
      
      
      Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
      removes the duplicate io_policies and functions definition.
      
      This patch:
      - replace arm_io_storage.c with the content of arm_fconf_io_storage.c
      - rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB.
      - use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb.
      - propagate DEFINES when parsing dts.
      - use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb.
      - set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior
        of fvp stays the same as it was before the introduction of fconf.
      
      Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e
      Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      a6de824f
  28. 11 Mar, 2020 2 commits
    • Madhukar Pappireddy's avatar
      fconf: necessary modifications to support fconf in BL31 & SP_MIN · 26d1e0c3
      Madhukar Pappireddy authored
      
      
      Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN.
      Created few populator() functions which parse HW_CONFIG device tree
      and registered them with fconf framework. Many of the changes are
      only applicable for fvp platform.
      
      This patch:
      1. Adds necessary symbols and sections in BL31, SP_MIN linker script
      2. Adds necessary memory map entry for translation in BL31, SP_MIN
      3. Creates an abstraction layer for hardware configuration based on
         fconf framework
      4. Adds necessary changes to build flow (makefiles)
      5. Minimal callback to read hw_config dtb for capturing properties
         related to GIC(interrupt-controller node)
      6. updates the fconf documentation
      
      Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af
      Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      26d1e0c3
    • Madhukar Pappireddy's avatar
      fconf: enhancements to firmware configuration framework · 25d740c4
      Madhukar Pappireddy authored
      
      
      A populate() function essentially captures the value of a property,
      defined by a platform, into a fconf related c structure. Such a
      callback is usually platform specific and is associated to a specific
      configuration source.
      For example, a populate() function which captures the hardware topology
      of the platform can only parse HW_CONFIG DTB. Hence each populator
      function must be registered with a specific 'config_type' identifier.
      It broadly represents a logical grouping of configuration properties
      which is usually a device tree source file.
      
      Example:
      > TB_FW: properties related to trusted firmware such as IO policies,
      	 base address of other DTBs, mbedtls heap info etc.
      > HW_CONFIG: properties related to hardware configuration of the SoC
      	 such as topology, GIC controller, PSCI hooks, CPU ID etc.
      
      This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate()
      to register and invoke the appropriate callbacks selectively based on
      configuration type.
      
      Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a
      Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      25d740c4
  29. 04 Mar, 2020 1 commit
    • Manish Pandey's avatar
      SPMD: loading Secure Partition payloads · cb3b5344
      Manish Pandey authored
      
      
      This patch implements loading of Secure Partition packages using
      existing framework of loading other bl images.
      
      The current framework uses a statically defined array to store all the
      possible image types and at run time generates a link list and traverse
      through it to load different images.
      
      To load SPs, a new array of fixed size is introduced which will be
      dynamically populated based on number of SPs available in the system
      and it will be appended to the loadable images list.
      
      Change-Id: I8309f63595f2a71b28a73b922d20ccba9c4f6ae4
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      cb3b5344