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The PCIe root port is outside of the current RPi
MMIO regions, so we need to adjust the address map.
Given much of the code depends on the legacy IOBASE
lets separate that from the actual MMIO begin/end.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Id65460ae58556bd8826dba08bbad79953e2a7c0b

Add some basic documentation and pointers for the SMCCC PCI
build options.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ia35f31d15066ea74135367cde2dce2f26e6ab31e

Add SMC wrappers for handshaking the existence
and basic parameter validation for the SMCCC/PCI
API. The actual read/write/segment validation is
implemented by a given platform which will enable
the API by defining SMC_PCI_SUPPORT.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: I4485ad0fe6003cec6f5eedef688914d100513c21

Add constants, structures and build definition for the
new standard SMCCC PCI conduit. These are documented
in DEN0115A.

https://developer.arm.com/documentation/den0115/latest

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: If667800a26b9ae88626e8d895674c9c2e8c09658

The SMCCC, part 3 indicates that only the bottom
32-bits of a 32-bit SMC call are valid. The upper
bits must be zero. Lets enforce that so standard
service code can assume its been called that way.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: I1bac50fbdc3b6ddca5fe2d1d1f96166a65ac4eb4

Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).

HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.

HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.

HW CRC calculation support will be used in the upcoming
firmware update patches.

Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Disable non-invasive debug of secure state for Juno
in release builds. This makes sure that PMU counts
only Non-secure events.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0d1c3f96f3b4e48360a7211ae55851d65d291025

* changes:
  docs(prerequisites): add `--no-save` to `npm install`
  fix(hooks): downgrade `package-lock.json` version

To avoid the mistake fixed by the previous commit, ensure users install
the Node.js dependencies without polluting the lock file by passing
`--no-save` to the `npm install` line.

Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1
Signed-off-by: Chris Kay <chris.kay@arm.com>

The NPM lock file was accidentally updated using a later version of
Node.js than required by the prerequisites. This upgraded the lock file
to the v2 format, which causes a warning on Node.js 14 (the
prerequisites version). This moves the lock file back to v1 by
installing the dependencies with Node.js 14.

Change-Id: I382d599fd2b67b07eb9234d14e7b631db6b11453
Signed-off-by: Chris Kay <chris.kay@arm.com>

Clean up instructions for building/running TF-A on the
Juno platform and add correct link to SCP binaries.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b

Updated the minor version in the makefile

Change-Id: Ie2b3ce5b36a105a0e2fff52c3740cc9702ca3108
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

An indirect dependency of Commitizen (`merge`) is currently failing the
NPM.js auditor due to vulnerability CVE-2020-28499. This commit moves
the minimum version of Commitizen to 4.2.4, which has resolved this
vulnerability.

Change-Id: Ia9455bdbe02f7406c1a106f173c4095943a201ed
Signed-off-by: Chris Kay <chris.kay@arm.com>

General refresh of the SPM document.

Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>

Change log for trusted-firmware-a v2.5 release

Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Removing the "Upcoming" change log due to the change in change log
processing.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5

In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.

As initrds are the most common and easy userland option for the boards,
let's increase the maximum size to the advertised 100 MB, to avoid
unpacking errors when an initrd exceeds the current limit of 20 MB.

Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.

Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

This is the first release of the public Trusted
Firmware A class threat model. This release
provides the baseline for future updates to be
applied as required by developments to the
TF-A code base.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11

Updated the list of supported FVP platforms as per the latest FVP
release.

Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

* changes:
  plat: imx8mp: change the bl31 physical load address
  plat: imx8m: Fix the macro define error

on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4

the 'always_on' member should be initialized from 'on'.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91

* changes:
  plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
  plat: ti: k3: board: Lets cast our macros
  plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
  plat: ti: k3: platform_def.h: Define the correct number of max table entries
  plat: ti: k3: board: lite: Increase SRAM size to account for additional table

This allows the the Matterhorn ELP Arm core to operate at its
designated OPP.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca