1. 12 Jul, 2018 2 commits
  2. 11 Jul, 2018 18 commits
  3. 10 Jul, 2018 5 commits
  4. 09 Jul, 2018 1 commit
  5. 06 Jul, 2018 2 commits
  6. 05 Jul, 2018 4 commits
  7. 04 Jul, 2018 4 commits
  8. 03 Jul, 2018 4 commits
    • Andre Przywara's avatar
      allwinner: Add Allwinner H6 SoC support · bed42a5d
      Andre Przywara authored
      
      
      The H6 is Allwinner's most recent SoC. It shares most peripherals with the
      other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
      map.
      
      Introduce a separate platform target, which includes a different header
      file to cater for the address differences. Also add the new build target
      to the documentation.
      
      The new ATF platform name is "sun50i_h6".
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      bed42a5d
    • Sandrine Bailleux's avatar
      Fix incorrect pointer conversion in SMC_UUID_RET() · 43b8fa8e
      Sandrine Bailleux authored
      
      
      Casting a pointer to a struct uuid into a pointer to uint32_t may
      result in a pointer that is not correctly aligned, which constitutes
      an undefined behaviour. In the case of TF, this also generates a data
      abort because alignment fault checking is enabled (through the SCTLR.A
      bit).
      
      This patch modifies the SMC_UUID_RET() macro to read the uuid
      structure without any pointer aliasing. A helper function then
      combines every set of 4 bytes into a 32-bit value suitable to be
      returned through the x0-x3 registers.
      
      This fixes a violation of MISRA rule 11.3.
      
      Change-Id: I53ee73bb4cb332f4d8286055ceceb6f347caa080
      Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      43b8fa8e
    • Sandrine Bailleux's avatar
      AArch32: Force compiler to align memory accesses · a9c4dde3
      Sandrine Bailleux authored
      Alignment fault checking is always enabled in TF (by setting the
      SCTLR.A bit). Thus, all instructions that load or store one or more
      registers have an alignment check that the address being accessed is
      aligned to the size of the data element(s) being accessed. If this
      check fails it causes an Alignment fault, which is taken as a Data
      Abort exception.
      
      The compiler needs to be aware that it must not emit load and store
      instructions resulting in unaligned accesses. It already is for
      AArch64 builds (see commit fa1d3712
      
       "Add -mstrict-align to the gcc
      options"), this patch does the same for AArch32 builds.
      
      Change-Id: Ic885796bc6ed0ff392aae2d49f3a13f517e0169f
      Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      a9c4dde3
    • Antonio Nino Diaz's avatar
      xlat v2: Update documentation · 5cff8823
      Antonio Nino Diaz authored
      
      
      Update documentation to reflect the current state of the library.
      
      Change-Id: Ic72f90ee322d2ebd6ea7f4296315700d6bc434e6
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      5cff8823