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  1. 10 Jul, 2021 4 commits
    • Pali Rohár's avatar
      fix(plat/marvell/a3k): Fix check for external dependences · 2baf5038
      Pali Rohár authored 
      

Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
      2baf5038
    • Pali Rohár's avatar
      fix(plat/marvell/a8k): Add missing build dependency for BLE target · 04738e69
      Pali Rohár authored 
      

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
dependency on $(MV_DDR_LIB) target which checks that variable
$(MV_DDR_PATH) is correctly set and ensures that make completes
compilation of mv-ddr-marvell tree.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47
      04738e69
    • Pali Rohár's avatar
      fix(plat/marvell/a8k): Correctly set include directories for individual targets · 559ab2df
      Pali Rohár authored 
      

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split them into variables:
* $(PLAT_INCLUDES) for all TF-A BL images
* BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image
* $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree

Include directory $(CURDIR)/drivers/marvell is required by TF-A BL
images, so move it from ble.mk to a8k_common.mk.

Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so
move it into BLE target specific $(PLAT_INCLUDES) variable.

And remaining include directories specified in ble.mk are needed only
for building external dependences from Marvell mv-ddr tree, so move them
into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB)
target.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67
      559ab2df
    • Pali Rohár's avatar
      fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set · 528dafc3
      Pali Rohár authored 
      

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.

TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.

So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
      528dafc3
  3. 08 Jul, 2021 2 commits
  5. 02 Jul, 2021 5 commits
  7. 30 Jun, 2021 2 commits
  9. 29 Jun, 2021 2 commits
    • Sandrine Bailleux's avatar
      refactor(plat/fvp): tidy up list of images to measure · 64dd1dee
      Sandrine Bailleux authored 
      

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

Also remove the GPT image type from the list, as it does not get
measured. GPT is a container, just like FIP is. We don't measure the FIP
but rather the images inside it. It would seem logical to treat GPT the
same way.

Besides, only images that get loaded through load_auth_image() get
measured right now. GPT processing happens before that and is handled in
a different way (see partition_init()).

Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      64dd1dee
    • Manish Pandey's avatar
      feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1 · 7285fd5f
      Manish Pandey authored 
      For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14b

Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
      7285fd5f
  11. 28 Jun, 2021 2 commits
  13. 22 Jun, 2021 3 commits
  15. 17 Jun, 2021 2 commits
  17. 15 Jun, 2021 5 commits
  19. 14 Jun, 2021 1 commit
    • Michal Simek's avatar
      feat(plat/zynqmp): extend DT description by TF-A · 0a8143dd
      Michal Simek authored 
      

In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can be (and should be) also protected by
protection unit XMPU. This is the first step to add reserved
memory location to DT.

DT address corresponds with default address in U-Boot and also
default address in Xilinx BSPs.

Code is valid only when TF-A runs out of DDR. When it runs out
of OCM there is no need to reseve anything because OCM is hidden
to OS.

Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      0a8143dd
  21. 12 Jun, 2021 2 commits
  23. 04 Jun, 2021 3 commits
  25. 03 Jun, 2021 5 commits
  27. 02 Jun, 2021 2 commits
    • Yann Gautier's avatar
      fix(plat/arm): correct UUID strings in FVP DT · 748bdd19
      Yann Gautier authored 
      

The UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined
in include/tools_share/firmware_image_package.h for BL32_EXTRA1 and
TRUSTED_KEY_CERT.
Signed-off-by: default avatarYann Gautier <yann.gautier@foss.st.com>
Change-Id: I517f8f9311585931f2cb931e0588414da449b694
      748bdd19
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART parent clock rate determination · 5a91c439
      Pali Rohár authored 
      

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
      5a91c439