- 18 Sep, 2019 1 commit
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Radoslaw Biernacki authored
This commit change the plat/qemu directory structure into: `-- plat `-- qemu |-- common (files shared with all qemu subplatforms) |-- qemu (original qemu platform) |-- qemu_sbsa (new sqemu_sbsa platform) |-- subplat1 `-- subplat2 This opens the possibility of adding new qemu sub-platforms which reuse existing common platform code. The first platform which will leverage new structure will be SBSA platform. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b
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- 09 Feb, 2018 1 commit
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Santeri Salko authored
Function plat_ic_get_pending_interrupt_type() should return interrupt type, not id. The function is used in aarch64 exception handling and currently the irq/fiq forwarding fails if a secure interrupt happens while running normal world. The qemu-specific gic file does not contain any extra functionality so it can be removed and common file can be used instead. fixes arm-software/tf-issues#546 Signed-off-by: Santeri Salko <santeri.salko@gmail.com>
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- 05 Feb, 2018 1 commit
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Etienne Carriere authored
Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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