- 13 Aug, 2021 1 commit
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Pali Rohár authored
Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation. Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function. Signed-off-by:Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
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- 16 Jul, 2021 1 commit
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Pali Rohár authored
INFO() macro for every call prepends "INFO: " string. Therefore current code prints unreadable debug messages: "INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0)INFO: " "INFO: Set IO decode window successfully, base(0xc000)INFO: win_attr(3d) max_dram_win(2) max_remap(0)INFO: win_offset(8)" Fix it by calling exactly one INFO() call for one line. After this change output is: "INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0) remap(0x0)" "INFO: Set IO decode window successfully, base(0xc000) win_attr(3d) max_dram_win(2) max_remap(0) win_offset(8)" Signed-off-by:
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- 11 Jul, 2021 2 commits
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Pali Rohár authored
For UART secure boot it is required also TIMN image, so pack it into uart-images.tgz.bin archive which is created by mrvl_uart target. $(TIMN_IMAGE) and $(TIM_IMAGE) variables are used only for UART images so their content needs to be initialized from $(TIMN_UART_CFG) and $(TIM_UART_CFG) config files. And not from $(TIMN_CFG) and $(TIM_CFG) as it is now because they are not generated during mrvl_uart target. Fix it to allow building mrvl_uart target before mrvl_flash target. To match usage of these variables, rename them to $(TIMN_UART_IMAGE) and $(TIM_UART_IMAGE). To not complicate rule for building uart-images.tgz.bin archive, set list of image files into a new $(UART_IMAGES) variable. Signed-off-by: -
Pali Rohár authored
For TIM config file use TIM name instead of DOIMAGE and use underscores to make variable names more readable. Signed-off-by:
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- 10 Jul, 2021 6 commits
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Pali Rohár authored
Armada 3700 uses external TBB tool for creating images and does not use internal TF-A doimage tool from tools/marvell/doimage/ Therefore set correct name of variable. Signed-off-by: -
Pali Rohár authored
Armada 3700 uses WTP so use WTP variable directly. Signed-off-by: -
Pali Rohár authored
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with latest TF-A code base. Marvell do not provide these old tarballs on Extranet anymore. Public version on github repository contains all patches and is working fine, so for public TF-A builds use only public external dependencies from git. Signed-off-by: -
Pali Rohár authored
BLE source files depend on external Marvell mv-ddr-marvell tree (specified in $(MV_DDR_PATH) variable) and its header files. Add dependency on $(MV_DDR_LIB) target which checks that variable $(MV_DDR_PATH) is correctly set and ensures that make completes compilation of mv-ddr-marvell tree. Signed-off-by: -
Pali Rohár authored
Do not set all include directories, including those for external targets in one PLAT_INCLUDES variable. Instead split them into variables: * $(PLAT_INCLUDES) for all TF-A BL images * BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image * $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree Include directory $(CURDIR)/drivers/marvell is required by TF-A BL images, so move it from ble.mk to a8k_common.mk. Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so move it into BLE target specific $(PLAT_INCLUDES) variable. And remaining include directories specified in ble.mk are needed only for building external dependences from Marvell mv-ddr tree, so move them into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB) target. Signed-off-by: -
Pali Rohár authored
Target mrvl_flash depends on external mv_ddr source code which is not part of TF-A project. Do not expect that it is pre-downloaded at some specific location and require user to specify correct path to mv_ddr source code via MV_DDR_PATH build option. TF-A code for Armada 37x0 platform also depends on mv_ddr source code and already requires passing correct MV_DDR_PATH build option. So for A8K implement same checks for validity of MV_DDR_PATH option as are already used by TF-A code for Armada 37x0 platform. Signed-off-by:
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- 02 Jun, 2021 1 commit
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Pali Rohár authored
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal clock can also run at 40 MHz (this is board specific). The frequency of the xtal clock is determined by a value on a strapping pin during SOC reset. The code to determine this frequency is already in A3K's comphy driver. Move the get_ref_clk() function from the comphy driver to a separate file and use it for UART parent clock rate determination. Signed-off-by:
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- 01 Jun, 2021 2 commits
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Pali Rohár authored
Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined to same values. De-duplicate them into PLAT_MARVELL_UART* macros. Signed-off-by: -
Pali Rohár authored
Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit d7c4420c ("plat/marvell: Migrate to multi-console API"). Remove them. Signed-off-by:
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- 28 May, 2021 1 commit
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Pali Rohár authored
UART parent clock is by default the platform's xtal clock, which is 25 MHz. The value defined in the driver, though, is 25.8048 MHz. This is a hack for the suboptimal divisor calculation Divisor = UART clock / (16 * baudrate) which does not use rounding division, resulting in a suboptimal value for divisor if the correct parent clock rate was used. Change the code for divisor calculation to Divisor = Round(UART clock / (16 * baudrate)) and change the parent clock rate value to 25 MHz. The final UART divisor for default baudrate 115200 is not affected by this change. (Note that the parent clock rate should not be defined via a macro, since the xtal clock can also be 40 MHz. This is outside of the scope of this fix, though.) Signed-off-by:
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- 27 Apr, 2021 1 commit
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Pali Rohár authored
This new compile option is only for Armada 3720 Development Board. When it is set to 1 then TF-A will setup PM wake up src configuration. By default this new option is disabled as it is board specific and no other A37xx board has PM wake up src configuration. Currently neither upstream U-Boot nor upstream Linux kernel has wakeup support for A37xx platforms, so having it disabled does not cause any issue. Prior this commit PM wake up src configuration specific for Armada 3720 Development Board was enabled for every A37xx board. After this change it is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1 Signed-off-by:
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- 20 Apr, 2021 12 commits
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Konstantin Porotchkin authored
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by:Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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Konstantin Porotchkin authored
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by:
sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by:
Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by:
Nadav Haklai <nadavh@marvell.com>
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Alex Evraev authored
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by:
Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by:
Stefan Chulski <stefanc@marvell.com> Reviewed-by:
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Konstantin Porotchkin authored
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by:
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Guo Yi authored
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by:
Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by:
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Konstantin Porotchkin authored
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by:
Ofer Heifetz <oferh@marvell.com> Reviewed-by:
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by:
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Alex Leibovich authored
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by:
Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by:
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Grzegorz Jaszczyk authored
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services. Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by:
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by:
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Konstantin Porotchkin authored
Wrong brakets caused MSS FW load timeout error: ERROR: MSS DMA failed (timeout) ERROR: MSS FW chunk 0 load failed ERROR: SCP Image load failed This patch fixes the operator precedence in MSS FW load. Signed-off-by:
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- 25 Feb, 2021 2 commits
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Konstantin Porotchkin authored
This patch cleans up the MSS SRAM if it was used for MSS image copy (secure boot mode). Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313 Signed-off-by:
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Konstantin Porotchkin authored
Map IO WIN to CP1 and CP2 at all stages including the BLE. Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly. This patch allows access to CP1/CP2 internal registers at BLE stage if CP1/CP2 are connected. Signed-off-by:
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- 24 Feb, 2021 1 commit
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Konstantin Porotchkin authored
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA. In secure boot mode the MSS DMA is unable to directly load the MSS FW image from DRAM to IRAM. This patch adds support for using the MSS SRAM as intermediate storage. The MSS FW image is loaded by application CPU into the MSS SRAM first, then transferred to MSS IRAM by MSS DMA. Such change allows the CP MSS image load in secure mode. Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712 Signed-off-by:
Grzegorz Jaszczyk <jaszczyk@marvell.com>
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- 11 Feb, 2021 2 commits
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Konstantin Porotchkin authored
The DRAM port code issues a dummy write to SPD page-0 i2c address in order to select this page for the forthcoming read transaction. If the write buffer length supplied to i2c_write is not zero, this call is translated to 2 bus transations: - set the target offset - write the data to the target However no actual data should be transferred to SPD page-0 in order to select it. Actually, the second transation never receives an ACK from the target device, which caused the following error report: ERROR: Status 30 in write transaction This patch sets the buffer length in page-0 select writes to zero, leading to bypass the data transfer to the target device. Issuing the target offset command to SPD page-0 address effectively selects this page for the read operation. Change-Id: I4bf8e8c09da115ee875f934bc8fbc9349b995017 Signed-off-by:
Moti Buskila <motib@marvell.com>
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Konstantin Porotchkin authored
Add initialization for TRNG-IP-76 driver and support SMC call 0xC200FF11 used for reading HW RNG value by secondary bootloader software for KASLR support. Signed-off-by:
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- 29 Jan, 2021 8 commits
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Pali Rohár authored
It does not have to be supported by the current shell used in Makefile. Replace it by a simple echo with implicit newline. Signed-off-by: -
Pali Rohár authored
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Pali Rohár authored
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Pali Rohár authored
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Pali Rohár authored
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Pali Rohár authored
This change separates building of flash and UART images, so it is possible to build only one of these images. Also this change allows make to build them in parallel. Target mrvl_flash now builds only flash image and mrvl_uart only UART image. This change reflects it also in the documentation. Signed-off-by: -
Pali Rohár authored
This removes need to move files and also allows to build uart and flash images in parallel. Signed-off-by: -
Pali Rohár authored
Currently a3700_common.mk makefile builds intermediate files in TF-A top level directory and also outside of the TF-A tree. This change fixes this issue and builds all intermediate files in $(BUILD_PLAT) directory. Part of this change is also removal of 'rm' and 'mv' commands as there is no need to remove or move intermediate files from outside of the TF-A build tree. Signed-off-by:
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