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include/plat/arm/common isn't needed by them, and is removed to avoid
dependency on Arm platform code.

Change-Id: Id9fccba33326fd075b3d1029bf1e4b012dfa0483
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat/arm files should only be used by Arm platforms. If other platforms
use them, they create dependencies that can introduce problems when
updating Arm platforms.

This patch copies the needed code from Arm platforms so that poplar can
be independent from them.

Change-Id: I0b194f5bdb0377b8ccacbd400e021614c026c7fe
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

No functional changes.

Change-Id: I9b9f8d3dfde08d57706ad5450de6ff858a55ac01
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This patch enabled PIE for FVP when RESET_TO_BL31=1. The references
to BL31_BASE are replaced by BL31_START as being a symbol exported by
the linker, will create a dynamic relocation entry in .rela.dyn and
hence will be fixed up by dynamic linker at runtime. Also, we disable
RECLAIM_INIT_CODE when PIE is enabled as the init section overlay
creates some static relocations which cannot be handled by the
dynamic linker currently.

Change-Id: I86df1b0a8b2a8bbbe7c3f3c0b9a08c86c2963ec0
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

This patch makes use of mov_imm macro where possible to load
immediate values within ARM platform layer.

Change-Id: I02bc7fbc1fa334c9fccf76fbddf515952f9a1298
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

This patch adds a utility function to return
the address of a symbol. By default, the compiler
generates adr/adrp instruction pair to return
the reference and this utility is used to override
this compiler generated to code and use `ldr`
instruction.

This is needed for Position Independent Executable
when it needs to reference a symbol which is constant
and does not depend on the execute address of the
binary.

For example, on the FVP, the GICv3 register context is
stored in a secure carveout (arm_el3_tzc_dram) within
DDR and does not relocate with the BL image. Now if
BL31 is executing at a different address other than
the compiled address, using adrp/adr instructions to
reference this memory will not work as they generate an
address that is PC relative. The way to get around this
problem is to reference it as non-PC relative (i.e
non-relocatable location) via `ldr` instruction.

Change-Id: I5008a951b007144258121690afb68dc8e12ee6f7
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

This function is not related to Arm platforms and can be reused by other
platforms if needed.

Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

There are several platforms using arm_setup_page_tables(), which is
supposed to be Arm platform only. This creates several dependency
problems between platforms.

This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib
v2 makefile. This way it is possible to detect from C code which version
is being used and include the correct header.

The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and
moved to a common folder. This way, when in doubt, this header can be
used to guarantee compatibility, as it includes the correct header based
on XLAT_TABLES_LIB_V2.

This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so
that is now locked in xlat lib v2) and ZynqMP (where it was added as a
workaround).

Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

There seems to be a problem where SCP can't turn CPU0 off. Instead of
returning PSCI_E_DENIED or crashing make CPU0 wait in a WFE loop. This
way all CPUs have a consistent behaviour from the point of view of the
caller.

Change-Id: I5c8c266ca3b69c9e7a4f5ae70afeea5dd36a0825
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This works fine for CPU1-3, but it fails for CPU0, where it is simply
ignored and leaves CPU0 in a WFI loop.

Change-Id: I7d73683fdd894f2021d6a5bc2cce6cd03e18e633
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The Amlogic Meson S905 is a SoC with a quad core Arm Cortex-A53 running
at 1.5Ghz. It also contains a Cortex-M3 used as SCP.

This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux:

- Partial SCPI support.
- Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF).
- GICv2 driver set up.
- Basic SIP services (read efuse data, enable/disable JTAG).

This port has been tested in an ODROID-C2.

Change-Id: Ia4bc82d7aca42a69d6b118b947279f82b3f6c6da
Tested-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The default behaviour of the plat_crash_console_xxx functions isn't
obvious to someone that hasn't read all the documentation. As they are
not mandatory, it is unlikely that the code will be checked when doing a
platform port, which may mean that some platforms may not have crash
console support at all.

The idea of this patch is to force platform maintainers to decide how
the crash console has to behave so that the final behaviour isn't
unexpected.

Change-Id: I40b2a7b56c5530c1dcd63eace5bd37ae6335056e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This platform depends on weak functions defined in
``plat/common/aarch64/platform_helpers.S`` that are going to be removed.

Change-Id: I5104d091c32271d77ed9690e9dc257c061289def
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Platforms that wish to use the sample functions have to add the file to
their Makefile. It is not included by default.

Change-Id: I713617bb58dc218967199248f68da86241d7ec40
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

In Arm platforms the crash console doesn't print anything if the crash
happens early enough. This happens in all images, not only BL1. The
reason is that they the files ``plat/common/aarch64/platform_helpers.S``
and ``plat/arm/common/aarch64/arm_helpers.S``, and the crash console
functions are defined as weak in both files. In practice, the linker
can pick the one in ``plat/common``, which simply switches the multi
console to crash mode when it wants to initialize the crash console.
In the case of Arm platforms, there are no console drivers registered
at that point, so nothing is printed.

This patch makes the functions in plat/arm strong so that they override
the weak functions in plat/common.

Change-Id: Id358db7d2567d7df0951790a695636cf6c9ac57f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Even though at this point plat_crash_console_flush is optional, it will
stop being optional in a following patch.

The console driver of warp7 doesn't support flush, so the implementation
is a placeholder.

TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but
they weren't global so they weren't actually used. Also, they were
calling the wrong functions.

imx8_helpers.S only has placeholders for all of the functions.

Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Non-Arm platforms shouldn't use Arm platform code. This patch copies the
implementation of the functions in arm_helpers.S to zynqmp_helpers.S to
remove this dependency of zynqmp on Arm platforms.

Change-Id: Ia85f303c4c63bcf0ffa57c7f3ef9d88376729b6b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the memory reserved for the Trusted Firmware, pass it on the DTB.

The current code deletes the memory reserved for the default bootstrap
of the Raspberry Pi and adds the region used by the Trusted Firmware.

This system replaces the previous one consisting on adding
``memmap=16M$256M`` to the Linux command line. It's also meant to be
used by U-Boot and any other bootloader that understands DTB files.

Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Version 1.4.7 of libfdt is bigger than the current one (1.4.2) and the
current reserved space for BL2 in Juno isn't enough to fit the Trusted
Firmware when compiling with clang or armclang.

Change-Id: I7b73394ca60d17f417773f56dd5b3d54495a45a8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.

Also, fix some address definitions in arm_def.h.

Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM cores,
but runs on a separate power domain. This is meant to handle power
management with the ARM cores off.
There are efforts to run sophisticated firmware on that core
(communicating via SCPI with the ARM world), but for now can use it for
the rather simple task of helping to turn the ARM cores off. As this
cannot be done by ARM code itself (because execution stops at the
first of the three required steps), we can offload some instructions to
this management processor.
This introduces a helper function to hand over a bunch of instructions
and triggers execution. We introduce a bakery lock to avoid two cores
trying to use that (single) arisc core. The arisc code is expected to
put itself into reset after is has finished execution.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To avoid this situation, delay the activation of the DC1SW line until
the very end, so those other lines are always activated earlier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.

To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compatible string to find the PMIC node.
- We switch the N_VBUSEN pin if the DT property tells us so.
- We scan over all regulator subnodes, and switch DC1SW if there is at
least one other node referencing it (judging by the existence of a
phandle property in that subnode).
This is just the first part of the setup, a follow up patch will setup
voltages.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use the
information contained therein to setup some initial power rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The initial PMIC setup for the Allwinner platform is quite board
specific, and used to be guarded by reading the .dtb stub *name* from the
SPL image in the legacy ATF port. This doesn't scale particularly well,
and requires constant maintainance.
Instead having the actual .dtb available would be much better, as the PMIC
setup requirements could be read from there directly.
The only available BL33 for Allwinner platforms so far is U-Boot, and
fortunately U-Boot comes with the full featured .dtb, appended to the
end of the U-Boot image.

Introduce some code that scans the beginning of the BL33 image to look
for the load address, which is followed by the image size. Adding those
two values together gives us the end of the image and thus the .dtb
address. Verify that this heuristic is valid by sanitising some values
and checking the DTB magic.

Print out the DTB address and the model name, if specified in the root
node.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC,
which allows to programmatically power down the board.

Use the newly introduced RSB driver to detect and program the PMIC on
boot, then later to turn off the main voltage rails when receiving a
PSCI SYSTEM_POWER_OFF command.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

In the H6 platform code there is a routine to do the platform
initialisation of the R_I2C controller. We will need a very similar
setup routine to initialise the RSB controller on the A64.

Move this code to sunxi_common.c and generalise it to support all SoCs
and also to cover the related RSB bus.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Allwinner produces reference board designs, which apparently most board
vendors copy from. So every H5 board I checked uses regulators which are
controlled by the same PortL GPIO pins to power the ARM CPU cores, the
DRAM and the I/O ports.
Add a SoC specific power down routine, which turns those regulators off
when ATF detects running on an H5 SoC and the rich OS triggers a
SYSTEM_POWEROFF PSCI call.

NOTE: It sounds very tempting to turn the CPU power off, but this is not
working as expected, instead the system is rebooting. Most probably this
is due to VCC-SYS also being controlled by the same GPIO line, and
turning this off requires an elaborate and not fully understood setup.
Apparently not even Allwinner reference code is turning this regulator
off. So for now we refrain to pulling down PL8, the power consumption is
quite low anyway, so we are as close to poweroff as reasonably possible.
Many thanks to Samuel for doing some research on that topic.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Many boards without a dedicated PMIC contain simple regulators, which
can be controlled via GPIO pins.

To later allow turning them off easily, introduce a simple function to
configure a given pin as a GPIO out pin and set it to the desired level.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.

So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.

This will be used in follow up patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Some boards don't have a PMIC, so they can't easily turn their power
off. To cover those boards anyway, let's turn off as many devices and
clocks as possible, so that the power consumption is reduced. Then
halt the last core, as before.
This will later be extended with proper PMIC support for supported
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

In the BL31 platform setup we read the Allwinner SoC ID to identify the
chip and print its name.
In addition to that we will need to differentiate the power setup
between the SoCs, to pass on the SoC ID to the PMIC setup routine.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

We will soon make more use of the Allwinner SoC ID, to differentiate the
platform setup.
Introduce definitions to avoid dealing with magic numbers and make the
code more readable.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part
ending at 0x117fff (although with gaps in between).
So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000.

Fix this to map the arisc exception vector area, which we will need
shortly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

According to the documentation, platforms may choose to trade memory
footprint for performance (and elegancy) by not providing a separately
mapped coherent page.

Since a debug build is getting close to the SRAM size limit already, this
allows us to save about 3.5KB of BSS and have some room for future
enhancements.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For the two different platforms we support in the Allwinner port we
mostly rely on header files covering the differences. This leads to the
platform.mk files in the respective directories to be almost identical.

To avoid further divergence and make sure that one platform doesn't
break accidentally, let's create a shared allwinner-common.mk file and
include that from the platform directory.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The `finish_console_register` macro is used by the multi console
framework to register the `console_t` driver callbacks. It relied
on weak references to the `ldr` instruction to populate 0 to the
callback in case the driver has not defined the appropriate
function. Use of `ldr` instruction to load absolute address to a
reference makes the binary position dependant. These instructions
should be replaced with adrp/adr instruction for position independant
executable(PIE). But adrp/adr instructions don't work well with weak
references as described in GNU ld bugzilla issue 22589.

This patch defines a new version of `finish_console_register` macro
which can spcify which driver callbacks are valid and deprecates the
old one. If any of the argument is not specified, then the macro
populates 0 for that callback. Hence the functionality of the previous
deprecated macro is preserved. The USE_FINISH_CONSOLE_REG_2 define
is used to select the new variant of the macro and will be removed
once the deprecated variant is removed.

All the upstream console drivers have been migrated to use the new
macro in this patch.

NOTE: Platforms be aware that the new variant of the
`finish_console_register` should be used and the old variant is
deprecated.

Change-Id: Ia6a67aaf2aa3ba93932992d683587bbd0ad25259
Signed-off-by: Soby Mathew <soby.mathew@arm.com>