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A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is enabled, more information about the faulty access
(address, NSAID, type of access) is displayed.

Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

BIT24 of IPI command header is used to determine if caller is
secure or non-secure.

Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267

Merge "Bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled" into integration

Typically, interrupts for a specific security state get handled in the
same security execption level if the execution is in the same security
state. For example, if a non-secure interrupt gets fired when CPU is
executing in NS-EL2 it gets handled in the non-secure world.

However, interrupts belonging to the opposite security state typically
demand a world(context) switch. This is inline with the security
principle which states a secure interrupt has to be handled in the
secure world. Hence, the TSPD in EL3 expects the context(handle) for a
secure interrupt to be non-secure and vice versa.

The function "tspd_sel1_interrupt_handler" is the handler registered
for S-EL1 interrupts by the TSPD. Based on the above assumption, it
provides an assertion to validate if the interrupt originated from
non-secure world and upon success arranges entry into the TSP at
'tsp_sel1_intr_entry' for handling the interrupt.

However, a race condition between non-secure and secure interrupts can
lead to a scenario where the above assumptions do not hold true and
further leading to following assert fail.

This patch fixes the bug which causes this assert fail:

	ASSERT: services/spd/tspd/tspd_main.c:105
	BACKTRACE: START: assert
	0: EL3: 0x400c128
	1: EL3: 0x400faf8
	2: EL3: 0x40099a4
	3: EL3: 0x4010d54
	BACKTRACE: END: assert

Change-Id: I359d30fb5dbb1429a4a3c3fff37fdc64c07e9414
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

The UEFI specification details the represenatation
for the EFI_GUID type. Add this representation to the
uuid_helper_t union type so that GUID definitions
can be shared verbatim between UEFI and TF-A header
files.

Change-Id: Ie44ac141f70dd0025e186581d26dce1c1c29fce6
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>

1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
  In order to avoid referencing the released space on the stack when maybe MISUSED,
  it`s better to use global variables to store mmc_device_info in mmc.c
2.Delete redundant;

Signed-off-by: deqi.hu@siengine.com
Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc

* changes:
  SPM: declare third cactus instance as UP SP
  SPMD: lock the g_spmd_pm structure
  FF-A: implement FFA_SECONDARY_EP_REGISTER

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6

* changes:
  plat: tc0: add matterhorn_elp_arm library to tc0
  cpus: add Matterhorn ELP ARM cpu library

The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0

Add a lock and spin lock/unlock calls when accessing the fields of the
SPMD PM structure.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9bab705564dc1ba003c29512b1f9be5f126fbb0d

Remove the former impdef SPMD service for SPMC entry point
registration. Replace with FFA_SECONDARY_EP_REGISTER ABI
providing a single entry point address into the SPMC for
primary and secondary cold boot.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I067adeec25fc12cdae90c15a616903b4ac4d4d83

* changes:
  plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
  plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf

Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com>

* changes:
  qemu/qemu_sbsa: fix memory type of secure NOR flash
  qemu/qemu_sbsa: spm_mm supports 512 cores

Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e

When bit 20 of TZC400 Fail control register [1] is set to 1, it means
Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and
FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this.

 [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en



Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e

when updata routing of an SDEI event, if the registration flags
is SDEI_REGF_RM_PE, need to updata the affinity of shared event.
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Change-Id: Ie5d7cc4199253f6af1c28b407f712caac3092d06

* changes:
  drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
  drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
  drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
  drivers/gicv3: fix logical issue for num_eints
  drivers/gicv3: fix potential GICD context override with ESPI enabled
  drivers/gicv3: use mpidr to probe GICR for current CPU

Make the aarch64's el3_panic() function print a newline character after
PC address, otherwise the output can get mangled in one line with output
from other firmware. Here is an example of how the output of el3_panic()
got mangled with Linux' console output:

    ERROR:   Unhandled External Abort received on 0x80000001 at EL3!
    ERROR:    exception reason=1 syndrome=0x92000210
    PANIC at PC : 0x0000000004027400[13438.473133] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
    [13438.479255] rcu:     1-...0: (4 ticks this GP) idle=35e/1/0x4000000000000000 softirq=146459/146459 fqs=2625

The aarch32 version of this function already does this.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9f0d032c6cd1e2be7a1837f9c8e8244d30633993

* changes:
  mediatek: mt8192: Add Vcore DVFS driver
  mediatek: mt8192: Add SPM suspend driver
  mediatek: mt8192: supports mcusys off when system suspend
  mediatek: mt8192: Add lpm driver

1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a

Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

Supports dram/mainpll/26m off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2