- 02 Aug, 2021 1 commit
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Manish V Badarkhe authored
Added the build options used in defining the firmware update metadata structure. Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 27 Jul, 2021 1 commit
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Pali Rohár authored
Update documentation and group platform specific build options into their own subsections. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I05927d8abf9f811493c49b856f06329220e7d8bb
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- 24 Jul, 2021 1 commit
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Peng Fan authored
Add myself as i.MX8 maintainer. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58
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- 22 Jul, 2021 1 commit
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Abdellatif El Khlifi authored
This commit enables trusted-firmware-a with Trusted Board Boot support for the Diphda 64-bit platform. Diphda uses a FIP image located in the flash. The FIP contains the following components: - BL2 - BL31 - BL32 - BL32 SPMC manifest - BL33 - The TBB certificates The board boot relies on CoT (chain of trust). The trusted-firmware-a BL2 is extracted from the FIP and verified by the Secure Enclave processor. BL2 verification relies on the signature area at the beginning of the BL2 image. This area is needed by the SecureEnclave bootloader. Then, the application processor is released from reset and starts by executing BL2. BL2 performs the actions described in the trusted-firmware-a TBB design document. Signed-off-by: Rui Miguel Silva <rui.silva@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
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- 19 Jul, 2021 1 commit
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johpow01 authored
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some revisions of the V1 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r1p1 but this workaround only applies to revisions r1p0 - r1p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
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- 17 Jul, 2021 1 commit
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Rex-BC Chen authored
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be
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- 16 Jul, 2021 1 commit
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johpow01 authored
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
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- 12 Jul, 2021 2 commits
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Manish V Badarkhe authored
Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Julius Werner authored
The two existing plat/rockchip code owners seem to be no longer active in the project and are not responding to reviews. There have been a couple of small fixup patches[1][2][3] pending for months that couldn't be checked in for lack of Code-Owner-Review+1 flag. Add myself to the code owner list to unblock this bottleneck (I have been deeply involved in the rk3399 port, at least, so I know most of the code reasonably well). [1] https://review.trustedfirmware.org/9616 [2] https://review.trustedfirmware.org/9990 [2] https://review.trustedfirmware.org/10415 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic7b2bb73c35a9bea91ff46ee445a22819d2045d9
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- 10 Jul, 2021 2 commits
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Pali Rohár authored
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with latest TF-A code base. Marvell do not provide these old tarballs on Extranet anymore. Public version on github repository contains all patches and is working fine, so for public TF-A builds use only public external dependencies from git. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
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Pali Rohár authored
Target mrvl_flash depends on external mv_ddr source code which is not part of TF-A project. Do not expect that it is pre-downloaded at some specific location and require user to specify correct path to mv_ddr source code via MV_DDR_PATH build option. TF-A code for Armada 37x0 platform also depends on mv_ddr source code and already requires passing correct MV_DDR_PATH build option. So for A8K implement same checks for validity of MV_DDR_PATH option as are already used by TF-A code for Armada 37x0 platform. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
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- 30 Jun, 2021 1 commit
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Pankaj Gupta authored
Add maintainer entry for NXP platform code Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Idd5407b8a9c1aa50ba812b2b1a7ce45e8fac5027
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- 29 Jun, 2021 2 commits
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Sandrine Bailleux authored
Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Manish Pandey authored
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode. The underlying changes for enabling PIE in aarch32 is submitted in commit 4324a14b Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
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- 28 Jun, 2021 1 commit
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Max Shvetsov authored
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD. ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the platform. SVE is configured during initial setup and then uses EL3 context save/restore routine to switch between SVE configurations for different contexts. Reset value of CPTR_EL3 changed to be most restrictive by default. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
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- 23 Jun, 2021 2 commits
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johpow01 authored
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and r1p0 of the A78 processor core, it is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/603e3733492bde1625aa8780 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
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johpow01 authored
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0, and r1p1 of the A77 processor core, it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ib4b963144f880002de308def12744b982d3df868
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- 14 Jun, 2021 1 commit
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Yann Gautier authored
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux. Just copy the 2 files here. They both have MIT license which is accepted in TF-A. With this alignment, a new macro is added (GIC_CPU_MASK_SIMPLE). Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ib45174f35f1796ebb7f34af861b59810cfb808b0
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- 08 Jun, 2021 1 commit
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Jacky Bai authored
Due to the small OCRAM space used for TF-A, we will meet imx8mq build failure caused by too small RAM size. We CANNOT support it in TF-A CI. It does NOT mean that imx8mq will be dropped by NXP. NXP will still actively maintain it in NXP official release. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Iad726ffbc4eedc5f6770612bb9750986b9324ae9
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- 01 Jun, 2021 1 commit
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Zelalem authored
We currently use Linaro release software stack version 20.01 in the CI. Reflect that change in the docs. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173
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- 25 May, 2021 3 commits
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Madhukar Pappireddy authored
Two issues in documentation were identified after the release. This patch fixes these typos. 1. Matternhorn ELP CPU was made available through v2.5 release, not Matternhorn CPU 2. We had upgraded TF-A to use GCC 10.2 toolchain family and used this toolchain for release testing Change-Id: I33e59bb5a6d13f4d40dbb3352004d5b133431d65 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Jeremy Linton authored
Add some basic documentation and pointers for the SMCCC PCI build options. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Change-Id: Ia35f31d15066ea74135367cde2dce2f26e6ab31e
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Rex-BC Chen authored
Change owner for MediaTek platforms. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I60848a2c1b236cef61c2c22d8278197ad257b1c2
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- 17 May, 2021 1 commit
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Chris Kay authored
To avoid the mistake fixed by the previous commit, ensure users install the Node.js dependencies without polluting the lock file by passing `--no-save` to the `npm install` line. Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1 Signed-off-by: Chris Kay <chris.kay@arm.com>
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- 13 May, 2021 1 commit
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Zelalem authored
Clean up instructions for building/running TF-A on the Juno platform and add correct link to SCP binaries. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b
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- 12 May, 2021 1 commit
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Olivier Deprez authored
General refresh of the SPM document. Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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- 10 May, 2021 1 commit
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Davidson K authored
This patch adds support for the crypto and secure storage secure partitions for the Total Compute platform. These secure partitions have to be managed by Hafnium executing at S-EL2 Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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- 07 May, 2021 1 commit
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Madhukar Pappireddy authored
Change log for trusted-firmware-a v2.5 release Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 05 May, 2021 2 commits
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Zelalem authored
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I97b2c5c5cfbf4ddb055d0f7a5ab04386460db060
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laurenw-arm authored
Removing the "Upcoming" change log due to the change in change log processing. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5
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- 04 May, 2021 1 commit
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laurenw-arm authored
Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4 and Neoverse-N2x4. Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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- 30 Apr, 2021 3 commits
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Zelalem authored
This is the first release of the public Trusted Firmware A class threat model. This release provides the baseline for future updates to be applied as required by developments to the TF-A code base. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11
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laurenw-arm authored
Updated the list of supported FVP platforms as per the latest FVP release. Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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Olivier Deprez authored
PSA wording is not longer associated with FF-A. Change-Id: Id7c53b9c6c8f383543f6a32a15eb15b7749d8658 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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- 29 Apr, 2021 1 commit
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Manish V Badarkhe authored
Documented the build options used in Arm GPT parser enablement. Change-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 28 Apr, 2021 2 commits
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Madhukar Pappireddy authored
Updated tentative code freeze and release target date for v2.6 release. Change-Id: I3dd6cfef1a07f3e0159ec7996d18f6cbcb975da7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Madhukar Pappireddy authored
Updated code freeze and release target date for v2.5 release. Change-Id: I72850eed2aa77d3adecaf71d74e9ecebcc36d5b4 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 27 Apr, 2021 2 commits
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Pali Rohár authored
This new compile option is only for Armada 3720 Development Board. When it is set to 1 then TF-A will setup PM wake up src configuration. By default this new option is disabled as it is board specific and no other A37xx board has PM wake up src configuration. Currently neither upstream U-Boot nor upstream Linux kernel has wakeup support for A37xx platforms, so having it disabled does not cause any issue. Prior this commit PM wake up src configuration specific for Armada 3720 Development Board was enabled for every A37xx board. After this change it is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1 Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
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Aditya Angadi authored
A Neoverse reference design platform can have two or more variants that differ in core count, cluster count or other peripherals. To allow reuse of platform code across all the variants of a platform, introduce build option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design platforms. The range of allowed values for the build option is platform specific. The recommended range is an interval of non negative integers. An example usage of the build option is make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1 Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 26 Apr, 2021 1 commit
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Chris Kay authored
The `arm-gic.h` file distributed by the Linux kernel is disjunctively dual-licensed under the GPL-2.0 or MIT licenses, but the BSD-3-Clause license has been applied in violation of the requirements of both licenses. This change ensures the file is correctly licensed under the terms of the MIT license, and that we comply with it by distributing a copy of the license text. Change-Id: Ie90066753a5eb8c0e2fc95ba43e3f5bcbe2fa459 Signed-off-by: Chris Kay <chris.kay@arm.com>
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