- 15 Nov, 2018 1 commit
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Antonio Niño Díaz authored
SPM priority level changes
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- 14 Nov, 2018 3 commits
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Sughosh Ganu authored
The current secure partition design mandates that a) at a point, only a single core can be executing in the secure partition, and b) a core cannot be preempted by an interrupt while executing in secure partition. Ensure this by activating the SPM priority prior to entering the parition. Deactivate the priority on return from the partition. Change-Id: Icb3473496d16b733564592eef06304a1028e4f5c Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Register a priority level, PLAT_SP_PRI, for secure partition with EL3 exception handling framework(ehf) module. The secure partition manager(SPM) would raise the core's priority to PLAT_SP_PRI before entering the secure partition, to protect the core from getting interrupted while in secure partition. Change-Id: I686897f052a4371e0efa9b929c07d3ad77249e95 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Add a dependency for building EL3 exception handling framework(EHF) module with the secure partition manager(SPM). The EHF module is needed for raising the core's running priority before the core enters the secure partition, and lowering it subsequently on exit from the secure partition. Change-Id: Icbe2d0a63f00b46dc593ff3d86b676c9333506c3 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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- 13 Nov, 2018 2 commits
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Antonio Nino Diaz authored
Correct some issues found with static analysis tools
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Antonio Niño Díaz authored
cadence: uart: comply to console_register prototype
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- 12 Nov, 2018 3 commits
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Alexei Colin authored
Signed-off-by: Alexei Colin <acolin@isi.edu>
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Antonio Niño Díaz authored
hikey, hikey960, poplar: use new console APIs
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Antonio Niño Díaz authored
Add support new Xilinx Versal ACAP platform
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- 09 Nov, 2018 5 commits
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Yann Gautier authored
It is already in include/drivers/st/stm32mp1_ddr_helpers.h. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
These issues wer found by sparse: drivers/st/clk/stm32mp1_clk.c:1524:19: warning: incorrect type in assignment (different base types) expected restricted fdt32_t const [usertype] *pkcs_cell got unsigned int const [usertype] * plat/st/stm32mp1/plat_image_load.c:13:6: warning: symbol 'plat_flush_next_bl_params' was not declared. Should it be static? plat/st/stm32mp1/plat_image_load.c:21:16: warning: symbol 'plat_get_bl_image_load_info' was not declared. Should it be static? plat/st/stm32mp1/plat_image_load.c:29:13: warning: symbol 'plat_get_next_bl_params' was not declared. Should it be static? plat/st/stm32mp1/bl2_io_storage.c:40:10: warning: symbol 'block_buffer' was not declared. Should it be static? Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
cppcheck: [drivers/partition/gpt.c:19] -> [drivers/partition/gpt.c:19]: (warning) Either the condition 'str_in!=((void*)0)' is redundant or there is possible null pointer dereference: name. sparse: drivers/partition/gpt.c:39:9: warning: Using plain integer as NULL pointer Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
These warnings were issued by sparse: plat/st/stm32mp1/stm32mp1_pm.c:365:36: warning: incorrect type in initializer (different modifiers) expected void ( *[noreturn] pwr_domain_pwr_down_wfi )( ... ) got void ( [noreturn] *<noident> )( ... ) plat/st/stm32mp1/stm32mp1_pm.c:366:23: warning: incorrect type in initializer (different modifiers) expected void ( *[noreturn] system_off )( ... ) got void ( [noreturn] *<noident> )( ... ) plat/st/stm32mp1/stm32mp1_pm.c:367:25: warning: incorrect type in initializer (different modifiers) expected void ( *[noreturn] system_reset )( ... ) got void ( [noreturn] *<noident> )( ... ) This cannot be changed the other way in all platforms pm drivers or else there is a compilation error: plat/st/stm32mp1/stm32mp1_pm.c:234:1: error: attributes should be specified before the declarator in a function definition Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Siva Durga Prasad Paladugu authored
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. This patch adds Virtual QEMU platform support for this SoC "versal_virt". Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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- 08 Nov, 2018 5 commits
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Jerome Forissier authored
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1. Enables building with ERROR_DEPRECATED=1. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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Jerome Forissier authored
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1. Enables building with ERROR_DEPRECATED=1. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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Jerome Forissier authored
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1. Enables building with ERROR_DEPRECATED=1. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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Antonio Niño Díaz authored
Standardise header guards across codebase
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Nov, 2018 6 commits
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Soby Mathew authored
Arm platforms: Fix DRAM address macros
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Soby Mathew authored
rcar_gen3: E3 target: fix compilation issues
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Soby Mathew authored
plat/arm: Fix MISRA defects in common code
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Soby Mathew authored
Remove unneeded _tzc_get_max_top_addr() function
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Soby Mathew authored
plat/arm: Support direct Linux kernel boot in AArch32
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Sandrine Bailleux authored
On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently 32-bit values (because they are suffixed with UL and the value 0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When summing them up, the result overflows the maximum value that can be encoded in a 32-bit value so it wraps around and does not result in the expected value. This patch changes the suffix of these constants into ULL so that they always are 64-bit values. Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 06 Nov, 2018 8 commits
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Sandrine Bailleux authored
This function was needed at the time where we didn't have the compiler_rt lib. An AArch32-specific variant was provided to handle the 64-bit shift operation in 32-bit. This is no longer needed. Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __aeabi_llsr() builtin, which is required by a subsequent patch that uses a logical right shift operator in AArch32. Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Antonio Nino Diaz authored
Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Niño Díaz authored
Introduce new fdt helpers
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ldts authored
Target builds but has not been tested. Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
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ldts authored
Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
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Soby Mathew authored
hikey: add delay after eMMC initialized
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- 05 Nov, 2018 1 commit
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Manish Pandey authored
This option allows the Trusted Firmware to directly jump to Linux kernel for aarch32 without the need of an intermediate loader such as U-Boot. Similar to AArch64 ARM_LINUX_KERNEL_AS_BL33 only available with RESET_TO_SP_MIN=1 as well as BL33 and DTB are preloaded in memory. Change-Id: I908bc1633696be1caad0ce2f099c34215c8e0633 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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- 02 Nov, 2018 6 commits
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Antonio Nino Diaz authored
fdtw_read_cells() can only read one or two cells, sometimes it may be needed to read more cells from one property. Change-Id: Ie70dc76d1540cd6a04787cde7cccb4d1bafc7282 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Introduced fdtw_read_string() to read string properties. Change-Id: I854eef0390632cf2eaddd2dce60cdb98c117de43 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I2f5f64aaf90caae936510e1179392a8835f493e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
From commit aafd1cf4235d78ce85b76d7da63e9589039344b3: - lib/libc/strlcpy.c Change-Id: Iaa7028fcc26706bdd6ee3f1e4bd55dd5873a30c6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Niño Díaz authored
plat: juno: fix build for !CSS_USE_SCMI_DRIVER
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Antonio Niño Díaz authored
Several MISRA defect fixes
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