1. 15 Jun, 2017 1 commit
  2. 12 May, 2017 1 commit
  3. 03 May, 2017 1 commit
  4. 01 May, 2017 2 commits
  5. 13 Apr, 2017 6 commits
  6. 10 Apr, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra: memctrl_v1: enable 'xlat_table_v2' library · c05a2197
      Varun Wadekar authored
      
      
      This patch enables the 'xlat_table_v2' library for the Tegra Memory
      Controller driver. This library allows us to dynamically map/unmap
      memory regions, with MMU enabled.
      
      The Memory Controller driver maps/unmaps non-overlapping Video Memory
      region, to clean it of any secure contents, before it resizes the
      region.
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c05a2197
  7. 07 Apr, 2017 5 commits
  8. 05 Apr, 2017 4 commits
  9. 30 Mar, 2017 5 commits
  10. 27 Mar, 2017 1 commit
  11. 23 Mar, 2017 3 commits
    • Varun Wadekar's avatar
      Tegra186: enable support for simulation environment · abd3a91d
      Varun Wadekar authored
      
      
      The Tegra simulation environment has limited capabilities. This patch
      checks the chip's major and minor versions to decide the features to
      enable/disable - MCE firmware version checking is disabled and limited
      Memory Controller settings are enabled
      
      Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      abd3a91d
    • Varun Wadekar's avatar
      Tegra186: save/restore BL31 context to/from TZDRAM · 68c7de6f
      Varun Wadekar authored
      
      
      This patch adds support to save the BL31 state to the TZDRAM
      before entering system suspend. The TZRAM loses state during
      system suspend and so we need to copy the entire BL31 code to
      TZDRAM before entering the state.
      
      In order to restore the state on exiting system suspend, a new
      CPU reset handler is implemented which gets copied to TZDRAM
      during boot. TO keep things simple we use this same reset handler
      for booting secondary CPUs too.
      
      Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      68c7de6f
    • Varun Wadekar's avatar
      Tegra186: re-configure MSS' client settings · e64ce3ab
      Varun Wadekar authored
      
      
      This patch reprograms MSS to make ROC deal with ordering of
      MC traffic after boot and system suspend exit. This is needed
      as device boots with MSS having all control but POR wants ROC
      to deal with the ordering. Performance is expected to improve
      with ROC but since no one has really tested the performance,
      keep the option configurable for now by introducing a platform
      level makefile variable.
      
      Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e64ce3ab
  12. 22 Mar, 2017 3 commits
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored
      
      
      This patch adds the chip level support for System Suspend entry
      and exit. As part of the entry sequence we first query the MCE
      firmware to check if it is safe to enter system suspend. Once
      we get a green light, we save hardware block settings and enter
      the power state. As expected, all the hardware settings are
      restored once we exit the power state.
      
      Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
    • Varun Wadekar's avatar
      Tegra186: memctrl_v2: restore video memory settings · ea96ac17
      Varun Wadekar authored
      
      
      The memory controller loses its settings when the device enters system
      suspend state.
      
      This patch adds a handler to restore the Video Memory settings in the
      memory controller, which would be called after exiting the system suspend
      state.
      
      Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ea96ac17
    • Varun Wadekar's avatar
      Tegra186: smmu: driver for the smmu hardware block · 4122151f
      Varun Wadekar authored
      
      
      This patch adds a device driver for the SMMU hardware block on
      Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
      Tegra186. The driver only supports saving the SMMU settings
      before entering system suspend. The MC driver and the NS world
      clients take care of programming their own settings.
      
      Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4122151f
  13. 20 Mar, 2017 7 commits
    • Varun Wadekar's avatar
      Tegra186: register FIQ interrupt sources · 50cd8646
      Varun Wadekar authored
      
      
      This patch registers all the FIQ interrupt sources during platform
      setup. Currently we support AON and TOP watchdog timer interrupts.
      
      Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50cd8646
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: implement MC txn override WAR · be87d920
      Varun Wadekar authored
      
      
      This patch sets the Memory Controller's TXN_OVERRIDE registers
      for most write clients to CGID_ADR. This ensures ordering is maintained.
      In some cases WAW ordering problems could occur. There are different
      settings for Tegra version A01 v A02.
      
      Original changes by Alex Waterman <alexw@nvidia.com>
      
      Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      be87d920
    • Varun Wadekar's avatar
      Tegra186: support for C6/C7 CPU_SUSPEND states · 7afd4637
      Varun Wadekar authored
      
      
      This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
      an idle state while C7 is a powerdown state.
      
      The MCE block takes care of the entry/exit to/from these core power
      states and hence we call the corresponding MCE handler to process
      these requests. The NS driver passes the tentative time that the
      core is expected to stay in this state as part of the power_state
      parameter, which we store in a per-cpu array and pass it to the
      MCE block.
      
      Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7afd4637
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: secure the on-chip TZSRAM memory · d48c0c45
      Varun Wadekar authored
      
      
      This patch programs the Memory controller's control registers
      to disable non-secure accesses to the TZRAM. In case these
      registers are already programmed by the BL2/BL30, then the
      driver just bails out.
      
      Change-Id: Ia1416988050e3d067296373060c717a260499122
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d48c0c45
    • Varun Wadekar's avatar
      Tegra186: support for the latest platform port handlers · b67a7c7c
      Varun Wadekar authored
      
      
      This patch adds support for the newer platform handler functions. Commit
      I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which
      has already moved all the upstream supported platforms over to these
      handler functions.
      
      Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      b67a7c7c
    • Varun Wadekar's avatar
      Tegra186: platform support for Tegra "T186" SoC · 3cf3183f
      Varun Wadekar authored
      
      
      Tegra186 is the newest SoC in the Tegra family which consists
      of two CPU clusters - Denver and A57. The Denver cluster hosts
      two next gen Denver15 CPUs while the A57 cluster hosts four ARM
      Cortex-A57 CPUs. Unlike previous Tegra generations, all the six
      cores on this SoC would be available to the system at the same
      time and individual clusters can be powered down to conserve
      power.
      
      Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e
      Signed-off-by: default avatarWayne Lin <wlin@nvidia.com>
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      3cf3183f
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: Memory Controller Driver (v2) · 412dd5c5
      Varun Wadekar authored
      
      
      This patch adds driver for the Memory Controller (v2) in the newer
      Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of
      the proprietary block in the past.
      
      Change-Id: I78359da780dc840213b6e99954e45e34428d4fff
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      412dd5c5