1. 27 Nov, 2013 4 commits
    • Sandrine Bailleux's avatar
      Unmask SError and Debug exceptions. · 3738274d
      Sandrine Bailleux authored
      Any asynchronous exception caused by the firmware should be handled
      in the firmware itself.  For this reason, unmask SError exceptions
      (and Debug ones as well) on all boot paths.  Also route external
      abort and SError interrupts to EL3, otherwise they will target EL1.
      
      Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
      3738274d
    • Sandrine Bailleux's avatar
      fvp: Remove unnecessary initializers · 204aa03d
      Sandrine Bailleux authored
      Global and static variables are expected to be initialised to zero
      by default.  This is specified by the C99 standard. This patch
      removes some unnecessary initialisations of such variables.
      
      It fixes a compilation warning at the same time:
        plat/fvp/bl31_plat_setup.c:82:3: warning: missing braces around
        initializer [-Wmissing-braces]
           section("tzfw_coherent_mem"))) = {0};
           ^
        plat/fvp/bl31_plat_setup.c:82:3: warning: (near initialization for
        ‘ns_entry_info[0]’) [-Wmissing-braces]
      
      Note that GCC should not have emitted this warning message in the
      first place.  The C Standard permits braces to be elided around
      subaggregate initializers.  See this GCC bug report:
      http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
      
      Change-Id: I13cb0c344feb9803bca8819f976377741fa6bc35
      204aa03d
    • Sandrine Bailleux's avatar
      Fix inlining of GIC helper functions · 27866d84
      Sandrine Bailleux authored
      Change-Id: I27aad560a5da21c0439f3ccc9dc07b026e7c6022
      27866d84
    • Sandrine Bailleux's avatar
      Move generic architectural setup out of blx_plat_arch_setup(). · c10bd2ce
      Sandrine Bailleux authored
      blx_plat_arch_setup() should only perform platform-specific
      architectural setup, e.g. enabling the MMU.  This patch moves
      generic architectural setup code out of blx_plat_arch_setup().
      
      Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6
      c10bd2ce
  2. 14 Nov, 2013 6 commits
    • James Morrissey's avatar
      Fix documentation issues in v0.2 release · ba3155bb
      James Morrissey authored
      Change-Id: I4e2a9daa97e3be3d2f53894f2ec7947ba6bb3a16
      ba3155bb
    • Harry Liebel's avatar
      Add Foundation FVP documentation · cff4e296
      Harry Liebel authored
      Change-Id: I5e47ba96e128d3a793517441f5a6c9f2ccbdfc66
      cff4e296
    • Harry Liebel's avatar
      Add GICv3 ITS to FDTs · 3498859b
      Harry Liebel authored
      - The interrupt addresses need to be updated to work.
      
      Change-Id: Icdd00177095ae9e4eb7b13718762f92e29b1465c
      3498859b
    • Harry Liebel's avatar
      Do not enable CCI on Foundation FVP · 30affd56
      Harry Liebel authored
      - The Foundation FVP only has one cluster and does not have
        CCI.
      
      Change-Id: If91e81ff72c52e448150089c4cfea3e4d6ae1232
      30affd56
    • Harry Liebel's avatar
      FDTs for v5.2 Foundation model · 43ef4f1e
      Harry Liebel authored
      - The Foundation FVP is a cut down version of the Base FVP and as
        such lacks some components.
      - Three FDTs are provided.
        fvp-foundation-gicv2legacy-psci:
          Use this when setting the Foundation FVP to use GICv2. In this
          mode the GIC is located at the VE location, as described in the
          VE platform memory map.
        fvp-foundation-gicv3-psci :
          Use this when setting the Foundation FVP to use GICv3. In this
          mode the GIC is located at the Base location, as described in the
          Base platform memory map.
        fvp-foundation-gicv2-psci :
          Use this when setting the Foundation FVP to use GICv3, but Linux
          is expected to use GICv2 emulation mode. In this mode the GIC is
          located at the Base location, but the GICv3 is used in GICv2
          emulation mode.
      
      Change-Id: I9d69bcef35c64cc8f16550efe077f578e55aaae5
      43ef4f1e
    • Harry Liebel's avatar
      Writing to the FVP LED register should be a 32bit access. · 068b950f
      Harry Liebel authored
      - Writing to this register with a 64bit access can cause a
        Systen Error Exception on some models.
      
      Change-Id: Ibcf5bdf7ab55707db61c16298f25caff50e1ff7e
      068b950f
  3. 25 Oct, 2013 1 commit