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This patch adds dependency rule generation and inclusion to the M0
Makefile, so that M0 objects will get correctly remade with an
incremental build if a header file they included changed.

Change-Id: I2067bd9fd4d9dad3e77a09cbf09c7b4db3c1eda5
Signed-off-by: Julius Werner <jwerner@chromium.org>

The dependencies in the M0 Makefile are not correctly laid out, which
may lead to errors with make -j if the binary target gets evaluated
before the target that creates the directory. In addition, the M0
Makefile just calls mkdir without using the platform-independent macros
from the main ARM TF build system. This patch fixes those issues,
removes some unused (and broken) M0 build targets and merges the two M0
output directories into one (since there's no real point splitting it up
and it creates more hassle).

Change-Id: Ia5002479cf9c57fea7aefa8ca88e373df3a51f61
Signed-off-by: Julius Werner <jwerner@chromium.org>

The RK3399 supports close the center logic enter power mode,
so we can close PD_CENTER to save more power during suspend.
Therefore, we need to support save/restore the DDR PHY and
controller registers during suspend/resume.

Also, need CL (http://crosreview.com/397399

) to check disabling
center logic.

Change-Id: I288defd8e9caa3846d9fa663a33e4d51df1aaa5d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This changes the style of dmc register accesses to be a read/write on
a base address plus a register offset instead of reinterpretting a
base address as a struct and accessing members within that struct.

Change-Id: Iead097cd6afdb830d8bc193608cd39d01ce5a6bc
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This renames dram.c and dram.h to dfs.c and dfs.h respectively. This
is to make room for common functionality between frequency scaling and
suspend code for the DRAM in a pair of common files named dram.c and
dram.h. It also removes a duplicate enum definition from
dram_spec_timing.h

Change-Id: Ibfa1041f8781401f9d27901fe8c61862bcb05562
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This moves the PMU register definitions into another file for use in
later patches.

Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Due to the PMU design, the PMU may not clear the WAKEUP bit after
wakeup, therefore, the state machine at the power mode may enter
the infinite loop during WFI.

There is a solution that we can use the M0 to monitor the WAKEUP
bit and clear it during power mode, then the state machine will be
recovered immediately. Then, the DUT can exit the WFI normally.

Change-Id: I303628553b728c214bf2d436bd3122032b5e669c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This CL supports add M0 source code to built into the bl31.bin, the
goal is that we can load the M0 code binary into SRAM and execute it.

We need the M0 help us to clean the power_mode_en bit during the AP
PMU enter the state machine with interrupt, and avoid to the AP can
not exit the loop forever.

Change-Id: I844582c54a1f0d44ca41290d44618df58679f341
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Add the common extra.ld.S and customized rk3399.ld.S to extend
to more features for different platforms.
For example, we can add SRAM section and specific address to
load there if we need it, and the common bl31.ld.S not need to
be modified.

Therefore, we can remove the unused codes which copying explicitly
from the function pmusram_prepare(). It looks like more clear.

Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

The CRU_CLKSEL_COUNT value is 108, not 0x108.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ib9db066b8b3ecafcee7f645dd5633b55a808e3d7

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.

Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529

We make sure the resuming of gic need to be enabled.
Otherwise, The resume will hit the below panic.
...
[   24.230541] CPU0: update max cpu_capacity 451
[   24.236029] CPU5: update max cpu_capacity 1024
[   24.236046] CPU4: shutdown
[   24.243205] psci: CPU4 killed.
[   24.258730] CPU5: shutdown
[   24.261472] psci: CPU5 killed.
[   24.270417] GIC: unable to set SRE (disabled at EL2), panic ahead
[   24.270417] cat[7801]: undefined instruction: pc=ffffffc0004e65d0
[   24.270417] Code: b0003940 91274400 97f871af d2801e00 (d5184600)
[   24.270417] Internal error: Oops - undefined instruction: 0 [#1] PREEMPT

Change-Id: Ie9542c8d5768ba0accfa073453da8bfe06d4f921

As the checkpatch reports the warning or error.

plat/rockchip/common/plat_pm.c:96:
ERROR: do not set execute permissions for source files
plat/rockchip/rk3399/drivers/pmu/pmu.c:294:
ERROR: do not set execute permissions for source files

plat/rockchip/common/plat_pm.c:286: WARNING: line over 80 characters
plat/rockchip/common/plat_pm.c:287: WARNING: line over 80 characters

Change-Id: Ib347da21c56551c31df3f90f03777b13c75d5c26

for compatible 32bit and 64bit, we use 0x82xxxxxx as function ID,
we modify SIP call function return value to 32 bit.

Change-Id: Ib99b03a9ea423853aaa296dcc634ee82c622a552

For save power cosumption, if gpio power supply shut down, we need to
set gpio2 ~ gpio4 to input and HiZ status when suspend, and recovery
they status when rusume. we do it base on apio pass from loader.

Change-Id: I59fd2395e5e37e63425472a39f519822c9197e4c

some specific board need to disable/enable specific gpio when
suspend/resume, so we add this function, bootloader can pass the
specific gpio, and we can handle these gpios in bl31 suspend/resuem
function.

Change-Id: I373b03ef9202ee4a05a2b9caacdfa01b47ee2177

We may need gpio pull mode later, so add this function.
Besides fix a set pull mode bug, and save gpio clock gate,
when operate the gpio, we will enable gpio clock, when
finish gpio operate, restore gpio clock gate status.

Change-Id: Ia1d602804f571a17f5ddc499908663b968b02974

As rk3399 reported the d8/octane scores drop 10% with cpu idle.
The root cause is thc cpu cluster enter the slow mode.
We don't need switch the clock to 24MHz if cpu cluster enter the
retention mode. In order to improve performance, it just needs for
cluster enter powering off mode.

Also, we shouldn't do anything for hlvl if the system is off.

Change-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119

For the PMU design, we don't expect to get the interrupts before enter
the power mode. Since that will cause the confusion for the state
machine in the power mode.

Change-Id: Id8dee79ae617a66271b5caf92caf35f520f45099

Change-Id: I986d64df9dc62354d50ccea0468b90f090a44160
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

If we don't enable the Schmitt trigger on the 32 kHz clock then systems
won't always resume from suspend properly.  Presumably anything else in
the system that relies on the 32 kHz clock also will have problems
without the Schmitt trigger enabled.

Enable it always since having the 32 kHz clock on GPIO0_A0 isn't
exactly an optional feature, so all boards using rk3399 will need this.

Change-Id: Idc18c6cd1adc5be5f60efd9cb805d83d5cd40129

add auto_pd_dis_freq parameter, we can pass a frequency from kernel
to disable or enable ddr auto power down function.

Change-Id: Ie30914701336c59047c380381c6b75dd76a89562

add dram driver, and kernel can through sip function talk to bl31 to
do ddr frequency scaling. and ddr auto powerdown.

Change-Id: I0d0f2869aed95e336c6e23ba96a9310985c84840

In a previous change we mistakenly thought that PMU_24M_EN_CFG directly
controlled whether the PMU counts ran off the 32k vs. 24M clock.
Apparently that's not true.  Real logic is now documented in code.

Also in the previous change we mistaknely though that PMU_24M_EN_CFG was
normally supposed to be 1 and we should "restore" it at resume time.
This is a terrible idea and made the system totally unreliable after
resume.  Apparently PMU_24M_EN_CFG should always be 0 with all the
current code and settings.

Let's fix the above two problems.  While we're changing all of this,
let's also:

1. Init at boot time.  Many of these counts are used when the system is
   running normally.  We want the behavior at boot to match the behavior
   after suspend/resume.

2. Init CPU counts to be 1 us.  Although old code was trying to set this
   to 1 ms (1000x slower) at suspend/resume time, we've been testing the
   kernel with 1 us for a long time now.  That's because the kernel (at
   boot time) set these values to 24.  Let's keep at 24 until we know
   that's wrong.

3. Init GPU counts to be 1 us.  Old code wasn't touching the GPU, but as
   documented in comments it makes sense to init here.  Do it.

4. Document the crap out of this code, since the SoC's behavior is
   confusing and poorly documented in the TRM.

5. Increase some stabilization times to 30 ms (from 3 ms).  It's unclear
   that a full 30 ms is needed, but let's be safe for now.

This also inits the counts for the GPU.

(Thanks to Doug's patch that come from https://crosreview.com/372381)

Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22

The pmusgrf reset-hold bits needs to be released, since the
pmusgrf reset-hold bits needs to be held.

Change-Id: Ia1eccc8fba18294f26b4cc07d47bc5e513dd9a1f

Sometimes this will cause the long delay for suspend/resume.
Since the 24M OCS will be turned off in power mode.
Also, remove the ERROR_DEPRECATED config define.

Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a

This patch updates some things for rk3399, as following:

1) Add the new file to handle the pwm. (e.g. the pwm regulator)
Make sure that good deal with the pwm related things.
Also, remove some pwm setting for pmu.c.

2) Set the plls slow mode and bypass in suspend, and restore them.

Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264

1. Remove the AP_PWROFF in ATF, should configure it in kernel.
2. Save and restore the PWMs pin/regs for suspend/resume.
3. The pmusgrf reset-hold bits needs to be released. since the
   pmusgrf reset-hold bits needs to be held.
4. Configure the PMU power up/down cycles about delay 3ms.
5. With the MMIO register block as one big mapping.
6. Fix the build error with psci_entrypoint since PSCI lib updated.

Fixes the commit
9ec78bdf ("rockchip: support the suspend/resume for rk3399").

Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264

1.Fixes the suspend/resume some bugs.
2.Add the power domain for saving power consumption.
3.Add cpu clusters suspend for rk3399 SoCs

Change-Id: Id602779016b41d6281f4ba40a20229d909b28e46

if define power off gpio, BL31 will do system power off through
gpio control.

If define a reset gpio, BL31 will use gpio to reset SOC,
otherwise use CRU reset.

There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.

This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.

Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a

This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This patch adds to support the RK3368 and RK3399 SoCs.

RK3368/RK3399 is one of the Rockchip family SoCs, which is an
multi-cores ARM SoCs.

This patch adds support to boot the Trusted Firmware on RK3368/RK3399
SoCs, and adds support to boot secondary CPUs, enter/exit core
power states for all CPUs in the slow/fast clusters.

This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs)
* Support arm gicv2 & gicv3.
* Boot up multi-cores CPU.
* Add generic CPU helper functions.
* Support suspend/resume.
* Add system_off & system_reset implementation.
* Add delay timer platform implementation.
* Support the new porting interface for the PSCI implementation.

Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>