- 10 Aug, 2020 1 commit
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Saurabh Gorecha authored
Adding support for QTI CHIP SC7180 on ATF Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
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- 06 Aug, 2020 1 commit
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Peng Fan authored
Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor could use SDEI to do hypervisor management, after physical IRQ has been disabled routing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5fd697fee22df151e13d0f1335e8ac8a7bae6189
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- 04 Aug, 2020 1 commit
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Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
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- 31 Jul, 2020 4 commits
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Alexei Fedorov authored
This patch fixes BL31 linker error "relocation R_AARCH64_ABS32 against `a local symbol' can not be used when making a shared object" when Position Independent Executable (PIE) support is enabled with ENABLE_PIE=1 build option. Change-Id: I2692269676db3f3b27eed499fc029fffb67969be Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Manish Pandey authored
Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
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Olivier Deprez authored
Following merge of patchset [1] the spm_mm_boot_info_t structure is included in few platform files unconditionally even when SPM_MM option is disabled. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2647 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I68bc034c9348b5d9bcfd2e5217b781df5ad1b369
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Nina Wu authored
- Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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- 30 Jul, 2020 4 commits
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Andre Przywara authored
The command line for BL33 payloads is typically taken from the DTB. On "normal" systems the bootloader will put the right version in there, but we typically don't use one on the FPGAs. To avoid editing (and possibly re-packaging) the DTB for every change in the command line, try to read it from some "magic" memory location instead. It can be easily placed there by the tool that uploads the other payloads to the FPGA's memory. BL31 will then replace the existing command line in the DTB with that new string. To avoid reading garbage, check the memory location for containing a magic value. This is conveniently chosen to be a simple ASCII string, so it can just preceed the actual command line in a text file: -------------------------------- CMD:console=ttyAMA0,38400n8 debug loglevel=8 -------------------------------- Change-Id: I5923a80332c9fac3b4afd1a6aaa321233d0f60da Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Olivier Deprez authored
Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
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Andre Przywara authored
N1SDP supports both single-chip and multi-chip environment. Added DTS file for both type of environment. Enabled DTS files compilation for N1SDP platform. Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0 Co-authored-by: Robin Murphy <Robin.Murphy@arm.com> Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com> Co-authored-by: Anurag Koul <anurag.koul@arm.com> Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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Manish Pandey authored
This patch fixes a bug where wrong panic was caused when the number of SP was same as max limit. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I9ace62d8d5bcdc410eeacdd9d33d55a7be5fcc8e
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- 26 Jul, 2020 3 commits
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Manish V Badarkhe authored
Enabled 'SMCCC_ARCH_SOC_ID' feature for Nvidia Tegra platforms. Change-Id: If17415f42304c6518aeead8dfe5909c378aaa777 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Currently, soc-revision information is not available for arm platforms hence disabled 'SMCCC_ARCH_SOC_ID' feature for all arm platforms. Change-Id: I1ab878c6a4c8fecfff63bc6dde83e3ecefe20279 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to be not correct for the platform which doesn't implement soc-id functionality i.e. functions to retrieve both soc-version and soc-revision. Hence introduced a platform function which will check whether SMCCC feature is available for the platform. Also, updated porting guide for the newly added platform function. Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 24 Jul, 2020 2 commits
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Manish Pandey authored
SPM(BL32) and hafnium(BL33) expect their manifest base address in x0 register, which is updated during BL2 stage by parsing fw_config. In case of RESET_TO_BL31 it has to be updated while populating entry point information. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I6f4a97f3405029bd6ba25f0935e2d1f74bb95517
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Javier Almansa Sobrino authored
As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
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- 23 Jul, 2020 5 commits
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Manish V Badarkhe authored
In BL2, fw_config's population happened before the cache gets enabled. Hence to boost the performance, moved fw_config's population after cache gets enabled (i.e. after MMU gets enabled). Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2e75cabd76b1cb7a660f6b72f409ab40d2877284
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Manish V Badarkhe authored
Updated the function 'set_fw_config_info' to make it generic by doing below changes: 1. Rename function name from 'set_fw_config_info' to 'set_config_info' 2. Take image_id as an argument so that this function can set any config information. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Icf29e19d3e9996d8154d84dbbbc76712fab0f0c1
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Manish V Badarkhe authored
Update the data type of the member 'config_max_size' present in the structure 'dyn_cfg_dtb_info_t' to uint32_t. This change is being done so that dyn_cfg_dtb_info_t and image_info structure should use same data type for maximum size. Change-Id: I9b5927a47eb8351bbf3664b8b1e047ae1ae5a260 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Currently, the need for firmware update is being checked twice in the code hence modifications are done to do this check only once and set the global variable. Then this global variable helps to decide whether to go for normal boot or firmware update flow. Change-Id: I8469284555a8039786f34670f9dc4830f87aecc1 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Renamed node for trusted boot fw config from 'plat_arm_bl2' to 'tb_fw-config'. Change-Id: I2e16b6f4d272292ec1855daafd014e851436dd9b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 22 Jul, 2020 2 commits
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Alexei Fedorov authored
This patch adds support for Measured Boot functionality to FVP platform code. It also defines new properties in 'tpm_event_log' node to store Event Log address and it size 'tpm_event_log_sm_addr' 'tpm_event_log_addr' 'tpm_event_log_size' in 'event_log.dtsi' included in 'fvp_tsp_fw_config.dts' and 'fvp_nt_fw_config.dts'. The node and its properties are described in binding document 'docs\components\measured_boot\event_log.rst'. Change-Id: I087e1423afcb269d6cfe79c1af9c348931991292 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Peng Fan authored
Implement IMX_SIP_AARCH32 to let AArch64 Bootloader could issue SIP call to switch to AArch32 mode to run OS. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I38b04ef909a6dbfba5ded12a7bb6e799a3935a66
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- 21 Jul, 2020 5 commits
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Alexei Fedorov authored
This patch adds support for Measured Boot driver functionality in BL1 and BL2 code. Change-Id: I7239a94c3e32b0a3e9e73768a0140e0b52ab0361 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Alexei Fedorov authored
This patch adds support for Event Log generation required for Measured Boot functionality. Change-Id: I34f05a33565e6659e78499d62cc6fb00b7d6c2dc Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Alexei Fedorov authored
This patch adds support for Measured Boot driver functionality in common Arm platform code. Change-Id: If049dcf8d847c39023b77c0d805a8cf5b8bcaa3e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Vijayenthiran Subramaniam authored
TBBR authentication framework depends on the plat_get_rotpk_info() function to return the pointer to the Root of Trust Public Key (ROTPK) stored in the platform along with its length. Add this function for RD-Daniel Config-XLR platform to support Trusted Board Boot. The function makes use of the wrapper function provided by the arm common trusted board boot function to get the ROTPK hash. Change-Id: I509e2f7e88cc2167e1732a971d71dc131d3d4b01 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Vijayenthiran Subramaniam authored
TBBR authentication framework depends on the plat_get_rotpk_info() function to return the pointer to the Root of Trust Public Key (ROTPK) stored in the platform along with its length. Add this function for RD-Daniel platform to support Trusted Board Boot. The function makes use of the wrapper function provided by the arm common trusted board boot function to get the ROTPK hash. Change-Id: I6c2826a7898664afea19fd62432684cfddd9319a Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 20 Jul, 2020 1 commit
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Alexei Fedorov authored
This patch moves all GICv2 driver files into new added 'gicv2.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. NOTE: Usage of 'drivers/arm/gic/common/gic_common.c' file is now deprecated and platforms with GICv2 driver need to be modified to include 'drivers/arm/gic/v2/gicv2.mk' in their makefiles. Change-Id: Ib10e71bdda0e5c7e80a049ddce2de1dd839602d1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 17 Jul, 2020 1 commit
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Andre Przywara authored
Getting the actual size of a DTB blob is useful beyond the Raspberry Pi port, so let's move this helper to a common header. Change-Id: Ia5be46e9353ca859a1e5ad9e3c057a322dfe22e2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 16 Jul, 2020 1 commit
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Etienne Carriere authored
This change implements platform services for stm32mp1 to expose clock and reset controllers over SCMI clock and reset domain protocols in sp_min firmware. Requests execution use a fastcall SMC context using a SiP function ID. The setup allows the create SCMI channels by assigning a specific SiP SMC function ID for each channel/agent identifier defined. In this change, stm32mp1 exposes a single channel and hence expects single agent at a time. The input payload in copied in secure memory before the message in passed through the SCMI server drivers. BL32/sp_min is invoked for a single SCMI message processing and always returns with a synchronous response message passed back to the caller agent. This change fixes and updates STM32_COMMON_SIP_NUM_CALLS that was previously wrongly set 4 whereas only 1 SiP SMC function ID was to be counted. STM32_COMMON_SIP_NUM_CALLS is now set to 3 since the 2 added SiP SMC function IDs for SCMI services. Change-Id: Icb428775856b9aec00538172aea4cf11e609b033 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 13 Jul, 2020 3 commits
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Manish Pandey authored
while mapping SPMC manifest page in the SPMD translation regime the mapped size was resolved to zero if SPMC manifest base address is PAGE aligned, causing SPMD to abort. To fix the problem change mapped size to PAGE_SIZE if manifest base is PAGE aligned. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I06cd39dbefaf492682d9bbb0c82b950dd31fb416
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Bharat Gooty authored
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Change-Id: I490d7e4d49bd9f5a62d343a264a1e14c2066ceca
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Roman Bacik authored
Change-Id: I4f5efcd7638a25c317382b51f05e6b9aa283d068 Signed-off-by: Roman Bacik <roman.bacik@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
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- 10 Jul, 2020 6 commits
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Manish V Badarkhe authored
BL2 size gets increased due to the libfdt library update and that eventually cause no-optimization build failure for BL2 as below: aarch64-none-elf-ld.bfd: BL2 image has exceeded its limit. aarch64-none-elf-ld.bfd: region `RAM' overflowed by 4096 bytes Makefile:1070: recipe for target 'build/fvp/debug/bl2/bl2.elf' failed make: *** [build/fvp/debug/bl2/bl2.elf] Error 1 Fixed build failure by increasing BL2 image size limit by 4Kb. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I92a57eb4db601561a98e254b64994bb921a88db3
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Grzegorz Jaszczyk authored
There is no need to open tree different IO window when there is possibility of having one covering required range. Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Marcin Wojtas authored
Update missing code releated to the BL32 payload. Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Konstantin Porotchkin authored
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module. It is followed by 4MB of shared memory. Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Now when mg_conf_cm3 driver is present - move all relevant code there. Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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