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No need to have a special SoC-specific prefix.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59

The header file is shared between all the SoCs. Better avoiding
hardcoding the SoC name in the function names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I9074871bd1ed8a702c1a656e0f50f2d3c6cb0425

The efuse driver is hardcoding the GXBB prefix. No need to do that since
the driver is shared between multiple SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I97691b0bbd55170d8216d301a3fc04feb8c2af2e

The code is the common directory is now generic, no need to have the SoC
prefix hardcoded in the function names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1

The SCPI code is the same between GXBB and GXL. No need to have it
replicated for each SoCs. Move it to the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I7e416caf1e9538b3ce7702c0363ee00a054e2451

Meson is the internal code name for the SoC family. The correct name for
the platform should be Amlogic. Change the name of the platform
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d

On Amlogic gxl (s905x) SOC, in order to use SCP, bl31 has to send bl30
and bl301 firmware along with their SHA256 hash over scpi.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>

The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running
at 1.5Ghz. It also contains a Cortex-M3 used as SCP.

This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux:

- Partial SCPI support.
- Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF).
- GICv2 driver set up.
- Basic SIP services (read efuse data, enable/disable JTAG).

This port has been tested on a lepotato.
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Remi Pommarel <repk@triplefau.lt>

The Amlogic Meson S905 is a SoC with a quad core Arm Cortex-A53 running
at 1.5Ghz. It also contains a Cortex-M3 used as SCP.

This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux:

- Partial SCPI support.
- Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF).
- GICv2 driver set up.
- Basic SIP services (read efuse data, enable/disable JTAG).

This port has been tested in an ODROID-C2.

Change-Id: Ia4bc82d7aca42a69d6b118b947279f82b3f6c6da
Tested-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>