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  1. 31 Jan, 2019 17 commits
    • Varun Wadekar's avatar
      Tegra: support for System Suspend using sc7entry-fw binary · 3ca3c27c
      Varun Wadekar authored 
      

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      3ca3c27c
    • Varun Wadekar's avatar
      Tegra210: remove support for cluster power down · 93e3b0f3
      Varun Wadekar authored 
      

This patch removes support for powering down a CPU cluster on
Tegra210 platforms as none of them actually use it.

Change-Id: I9665634cf2b5b7b8a1b5a2700cae152dc9165fe3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      93e3b0f3
    • Varun Wadekar's avatar
      Tegra210: support for cluster idle from the CPU · 7db077f2
      Varun Wadekar authored 
      

This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.

The CPU initates the cluster idle sequence on the last standing
CPU, by following these steps:

Entry
-----
* stop other CPUs from waking up
* program the PWM pinmux to tristate for OVR PMIC
* program the flow controller to enter CC6 state
* skip L1 $ flush during cluster power down, as L2 $ is inclusive
  of L1 $ on Cortex-A57 CPUs

Exit
----
* program the PWM pinmux to un-tristate for OVR PMIC
* allow other CPUs to wake up

This patch also makes sure that cluster idle state entry is not
enabled until CL-DVFS is ready.

Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7db077f2
    • Varun Wadekar's avatar
      Tegra: pmc: helper function to find last ON CPU · a7a63e0e
      Varun Wadekar authored 
      

This patch adds a helper function to find the last standing CPU
in a cluster.

Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      a7a63e0e
    • Steven Kao's avatar
      Tegra: platform dependent address space sizes · 1d11f73e
      Steven Kao authored 
      

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.

Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      1d11f73e
    • Varun Wadekar's avatar
      Tegra: organize memory/mmio apertures to decrease memmap latency · 26cf0849
      Varun Wadekar authored 
      

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.

Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      26cf0849
    • Varun Wadekar's avatar
      Tegra210: Enable WDT_CPU interrupt for FIQ Debugger · 51a5e593
      Varun Wadekar authored 
      

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      51a5e593
    • Varun Wadekar's avatar
      Tegra: flowctrl: helper functions to assist with cluster power states · 1483d4e0
      Varun Wadekar authored 
      

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate
* tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate
* tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU?

Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1483d4e0
    • Varun Wadekar's avatar
      Tegra: bpmp: remove bpmp init failed error print · fdb82faa
      Varun Wadekar authored 
      

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every cluster idle and powerdown request,
cluttering the logs.

Change-Id: I9e30007a913080406052fc32d5360ff70a019d75
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      fdb82faa
    • Varun Wadekar's avatar
      Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs · d16b045c
      Varun Wadekar authored 
      

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.

Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d16b045c
    • Varun Wadekar's avatar
      Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing · 2ed09b1e
      Varun Wadekar authored 
      

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.

This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.

Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2ed09b1e
    • Jeetesh Burman's avatar
      Tegra: SiP: set GPU in reset after vpr resize · 3e28e935
      Jeetesh Burman authored 
      

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      3e28e935
    • Varun Wadekar's avatar
      Tegra: handle FIQ interrupts when NS handler is not registered · 23ae8094
      Varun Wadekar authored 
      

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

Change-Id: Iebe952305f7db46375303699b6150611439475df
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      23ae8094
    • steven kao's avatar
      Tegra: bpmp_ipc: support to enable/disable module clocks · ff605ba2
      steven kao authored 
      

This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports SE devices.

Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90
Signed-off-by: default avatarsteven kao <skao@nvidia.com>
      ff605ba2
    • Varun Wadekar's avatar
      Tegra: fix offset used to dump GICD registers from crash handler · 8510376c
      Varun Wadekar authored 
      

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8510376c
    • Varun Wadekar's avatar
      Tegra: default platform handler for the CPU_STANDBY state · 0887026e
      Varun Wadekar authored 
      

This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with their own implementations.

Change-Id: I91e513842f194b1e2b1defa2d833bb4d9df5f06b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      0887026e
    • Pritesh Raithatha's avatar
      Tegra186: smmu: add support for backup multiple smmu regs · 28f45bb8
      Pritesh Raithatha authored 
      

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs that can be used for multiple
smmus.

Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      28f45bb8
  3. 29 Jan, 2019 6 commits
  5. 28 Jan, 2019 3 commits
  7. 25 Jan, 2019 9 commits
  9. 24 Jan, 2019 2 commits
  11. 23 Jan, 2019 3 commits