- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 15 Jun, 2017 1 commit
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Anthony Zhou authored
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Convert object type to match the type of function parameters [Rule 10.3] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 28 Feb, 2017 2 commits
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Varun Wadekar authored
This patch modifies the secure IRQ registration process to allow platforms to specify the target CPUs as well as the owner of the IRQ. IRQs "owned" by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted OS would return INTR_TYPE_S_EL1 as a result. Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a handler for FIQ interrupts triggered when the CPU is in the NS world. The handler stores the NS world's context along with ELR_EL3/SPSR_EL3. The NS world driver issues an SMC initially to register it's handler. The monitor firmware stores this handler address and jumps to it when the FIQ interrupt fires. Upon entry into the NS world the driver then issues another SMC to get the CPU context when the FIQ fired. This allows the NS world driver to determine the CPU state and call stack when the interrupt fired. Generally, systems register watchdog interrupts as FIQs which are then used to get the CPU state during hangs/crashes. Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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