1. 28 Sep, 2018 1 commit
  2. 15 Jun, 2017 1 commit
    • Anthony Zhou's avatar
      Tegra: fiq_glue: fix MISRA defects · 5bd1a177
      Anthony Zhou authored
      
      
      Main fixes:
      
      * Added explicit casts (e.g. 0U) to integers in order for them to be
        compatible with whatever operation they're used in [Rule 10.1]
      
      * Convert object type to match the type of function parameters
        [Rule 10.3]
      
      * Added curly braces ({}) around if statements in order to
        make them compound [Rule 15.6]
      
      * Expressions resulting from the expansion of macro parameters
        shall be enclosed in parentheses[Rule 20.7]
      
      Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b
      Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      5bd1a177
  3. 03 May, 2017 1 commit
  4. 28 Feb, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1 · 45eab456
      Varun Wadekar authored
      
      
      This patch modifies the secure IRQ registration process to allow platforms
      to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
      by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
      OS would return INTR_TYPE_S_EL1 as a result.
      
      Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      45eab456
    • Varun Wadekar's avatar
      Tegra: implement FIQ interrupt handler · 78e2bd10
      Varun Wadekar authored
      
      
      This patch adds a handler for FIQ interrupts triggered when
      the CPU is in the NS world. The handler stores the NS world's
      context along with ELR_EL3/SPSR_EL3.
      
      The NS world driver issues an SMC initially to register it's
      handler. The monitor firmware stores this handler address and
      jumps to it when the FIQ interrupt fires. Upon entry into the
      NS world the driver then issues another SMC to get the CPU
      context when the FIQ fired. This allows the NS world driver to
      determine the CPU state and call stack when the interrupt
      fired. Generally, systems register watchdog interrupts as FIQs
      which are then used to get the CPU state during hangs/crashes.
      
      Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      78e2bd10