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  1. 21 Apr, 2021 1 commit
  3. 02 Mar, 2021 1 commit
  5. 09 Feb, 2021 1 commit
  7. 03 Feb, 2021 1 commit
  9. 27 Jan, 2021 1 commit
  11. 19 Jan, 2021 1 commit
    • Ahmad Fatoum's avatar
      fdts: stm32mp1: add support for Linux Automation MC-1 board · 2fbb6064
      Ahmad Fatoum authored 
      

The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.

The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.

This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.

Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: default avatarAhmad Fatoum <a.fatoum@pengutronix.de>
      2fbb6064
  13. 14 Dec, 2020 2 commits
  15. 08 Dec, 2020 2 commits
  17. 23 Nov, 2020 2 commits
  19. 20 Oct, 2020 1 commit
  21. 13 Oct, 2020 1 commit
  23. 12 Oct, 2020 1 commit
  25. 08 Oct, 2020 1 commit
  27. 29 Sep, 2020 1 commit
    • Andre Przywara's avatar
      arm_fpga: Add devicetree file · b48883c7
      Andre Przywara authored 
      

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b48883c7
  29. 28 Sep, 2020 1 commit
  31. 24 Sep, 2020 1 commit
    • Yann Gautier's avatar
      fdts: stm32mp1: realign device tree with kernel · 277d6af5
      Yann Gautier authored 
      

There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A

The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.

There are 4 packages available, for which  the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.

STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.

Some reordering is done in other files, and realign with kernel DT files.

The DDR files are generated with our internal tool, no changes in the
registers values.

Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      277d6af5
  33. 22 Sep, 2020 1 commit
  35. 16 Sep, 2020 1 commit
  37. 08 Sep, 2020 1 commit
  39. 07 Sep, 2020 1 commit
  41. 28 Aug, 2020 1 commit
  43. 27 Aug, 2020 2 commits
  45. 31 Jul, 2020 1 commit
    • Manish Pandey's avatar
      tbbr/dualroot: rename SP package certificate file · 03a5225c
      Manish Pandey authored 
      

Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.

SP_CONTENT_CERT_ID is the certificate file which is currently generated
and signed with trusted world key which in-turn is derived from Silicon
provider RoT key.
To allow dual signing domain for SP packages, other certificate file
will be derived from Platform owned RoT key.

This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
does other related changes.
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
      03a5225c
  47. 30 Jul, 2020 2 commits
  49. 10 Jul, 2020 1 commit
  51. 06 Jul, 2020 1 commit
    • Abdellatif El Khlifi's avatar
      corstone700: splitting the platform support into FVP and FPGA · ef93cfa3
      Abdellatif El Khlifi authored 
      

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

  fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
  - Enabling NEED_BL33 option
  - Fixing non-secure image base: For no preloaded bl33 we want to
    have the NS base set on shared ram. Setup a memory map region
    for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: default avatarRui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      ef93cfa3
  53. 09 Jun, 2020 1 commit
  55. 03 Jun, 2020 2 commits
  57. 27 May, 2020 1 commit
    • Usama Arif's avatar
      plat/arm: Introduce TC0 platform · f5c58af6
      Usama Arif authored 
      

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      f5c58af6
  59. 19 May, 2020 1 commit
    • Alexei Fedorov's avatar
      FVP: Add support for passing platform's topology to DTS · 003faaa5
      Alexei Fedorov authored 
      

This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.

Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      003faaa5
  61. 15 May, 2020 1 commit
  63. 17 Apr, 2020 1 commit
  65. 24 Mar, 2020 1 commit
  67. 11 Mar, 2020 1 commit
    • Madhukar Pappireddy's avatar
      fconf: Extract topology node properties from HW_CONFIG dtb · 4682461d
      Madhukar Pappireddy authored 
      

Create, register( and implicitly invoke) fconf_populate_topology()
function which extracts the topology related properties from dtb into
the newly created fconf based configuration structure 'soc_topology'.
Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB
build feature.

A new property which describes the power domain levels is added to the
HW_CONFIG device tree source files.

This patch also fixes a minor bug in the common device tree file
fvp-base-gicv3-psci-dynamiq-common.dtsi
As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary
to delete all previous cluster node definitons because DynamIQ based
models have upto 8 CPUs in each cluster. If not deleted, the final dts
would have an inaccurate description of SoC topology, i.e., cluster0
with 8 or more core nodes and cluster1 with 4 core nodes.

Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      4682461d