- 07 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
-
- 17 Jul, 2019 1 commit
-
-
Hadi Asyrafi authored
Signed-off-by:
-
- 26 Feb, 2019 1 commit
-
-
Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:Loh Tien Hock <tien.hock.loh@intel.com>
-
- 04 Feb, 2019 1 commit
-
-
Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
-
