- 11 Sep, 2019 1 commit
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Carlo Caione authored
Make the header guards more generic and contextually remove the GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I842fa2e084e71280ae17b39c67877e844821a171
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- 05 Sep, 2019 23 commits
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Carlo Caione authored
Remove the GXBB prefix where needed and add SoC specific prefixes for GXBB/GXL. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27
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Carlo Caione authored
Remove the GXBB prefix from the code in the common directory and add SoC-specific prefixes in the SoC specific code. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030
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Carlo Caione authored
Add a new aml_* prefix to the SCPI related function calls. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739
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Carlo Caione authored
Make the MHU code AML specific adding a new aml_* prefix and remove the GXBB prefix from the register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2
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Carlo Caione authored
All the SIP/SVC related code is currently the same between GXL and GXBB. Rename function names and register names to avoid hardcoding the GXBB prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf
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Carlo Caione authored
No need to have a special SoC-specific prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59
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Carlo Caione authored
The header file is shared between all the SoCs. Better avoiding hardcoding the SoC name in the function names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I9074871bd1ed8a702c1a656e0f50f2d3c6cb0425
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Carlo Caione authored
The efuse driver is hardcoding the GXBB prefix. No need to do that since the driver is shared between multiple SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I97691b0bbd55170d8216d301a3fc04feb8c2af2e
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Carlo Caione authored
Fixing at the same time the related register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ib1130d50abe6088f1c0826878d1ae454a0f23008
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Carlo Caione authored
The code is the common directory is now generic, no need to have the SoC prefix hardcoded in the function names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1
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Carlo Caione authored
Now that every piece is in place, the makefiles can be refactored and slightly beautified removing useless and redundant parts. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: If74e1909df52d475cf4b0dfed819d07d3a4c85b9
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Carlo Caione authored
The code is the same between GXBB and GXL. Move it to the common source directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I875689a6fd029971aa755fc2725217e90ed06b6c
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Carlo Caione authored
As done already for multiple files, move the topology file to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Iaca357a089593ad58c35c05c929239132249dcda
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Carlo Caione authored
As for most of the Amlogic code, this is common between the Amlogic SoCs. Move the code to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Id3f0073ff1f0b9ddbe964f80303323ee4a2f27b0
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Carlo Caione authored
The MHU code is shared between all the supported platforms. Move it to the common directory instead. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Iaf53122866eae85c13f772927d16836dcfa877a3
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Carlo Caione authored
The efuse code is the same between GXL and GXBB. Move the code to common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ie37f21d1907a36292724f1fb645a78041fe4a6b3
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Carlo Caione authored
The platform macros are shared between all the SoCs. Move it to common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ia04c3ffe4d7b068aa701268ed99f69995d8db92b
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Carlo Caione authored
Now that also the SHA256 DMA driver is shared between all the SoCs, we can have one single private platform header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I77d51915f9d8233aeceeed66ed1f491573402cfc
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Carlo Caione authored
The SCPI code is the same between GXBB and GXL. No need to have it replicated for each SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e416caf1e9538b3ce7702c0363ee00a054e2451
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Carlo Caione authored
The SHA256 DMA driver can be used by multiple SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
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Carlo Caione authored
The assembly helpers are common to all the amlogic SoCs. Move the .S file to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I0d8616a7ae22dbcb14848cefd0149b6bb5814ea6
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Carlo Caione authored
Make the platform name a parameter for the source directories. Besides a cosmetic fix, this is going to be helpful when reusing the same Makefile for different SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I307897a21800cca8ad68a5ab8972d27e9356ff2a
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Carlo Caione authored
Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
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- 20 Aug, 2019 1 commit
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Manish Pandey authored
This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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- 19 Aug, 2019 3 commits
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Hadi Asyrafi authored
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
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Masahiro Yamada authored
Currently, console drivers prepend '\r' to '\n' by themselves. This is common enough to be supported in the framework. Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this flag to ask the framework to transform LF into CRLF instead of doing it by itself. Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
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- 16 Aug, 2019 3 commits
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Alexei Fedorov authored
SMMUv3 driver functions which are called from BL1 and BL31 currently use counter-based poll method for testing status bits. Adding Delay Timer driver to BL1 and BL31 is required for timeout-based implementation using timer delay functions for SMMU and other drivers. This patch adds new function `fvp_timer_init()` which initialises either System level generic or SP804 timer based on FVP_USE_SP804_TIMER build flag. In BL2U `bl2u_early_platform_setup()` function the call to `arm_bl2u_early_platform_setup()` (which calls `generic_delay_timer_init()` ignoring FVP_USE_SP804_TIMER flag), is replaced with `arm_console_boot_init()` and `fvp_timer_init()`. Change-Id: Ifd8dcebf4019e877b9bc5641551deef77a44c0d1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Marek Vasut authored
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate RCAR_PRODUCT_* macro. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96
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Marek Vasut authored
Pull out the PRR_* macros into rcar_def.h and remove multiple copies of it. Now that there are still RCAR_* macros in rcar_def.h too and they have the exact same meaning as the PRR_* macros, but that's for another patch. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc
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- 15 Aug, 2019 2 commits
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Ambroise Vincent authored
This patch updates all Tegra platforms to use the new multi console API. Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Julius Werner <jwerner@chromium.org>
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
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- 13 Aug, 2019 2 commits
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Louis Mayencourt authored
Change-Id: Ia1ecad58ebf9de3f3a44b17ad1de57424b431125 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Add the disable_auth dynamic parameter, that allows to disable the authentication when TBBR is enabled. This parameter is for development only. Change-Id: Ic24ad16738517f7e07c4f506dcf69a1ae8df7d2d Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 09 Aug, 2019 2 commits
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Heiko Stuebner authored
The rk3399 suspend code saves and restores the debug uart settings, but right now always does this for the default uart. Right now this works only by chance for the majority of rk3399 boards, which do not deviate from that default. But both Coreboot as well as U-Boot-based platforms can actually use different uarts for their output, which can be configured from either devicetree or Coreboot-variables. To fix this, just use the stored uart-base information instead of the default constant. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I1ea059d59a1126f6f8702315df7e620e632b686e
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Heiko Stuebner authored
Rockchip platforms can be booted from either u-boot or coreboot. So far the Coreboot-console was initizalized from a coreboot data struct in the early_param2 callbacks and dt-based consoles with data from the rockchip_get_uart_* functions. But later code may also need this console information for example for special suspend handling. To make this easy follow a suggestion from Julius Werner and move the coreboot<->dt distinction into the rockchip_get_uart_* functions, thus making correct data about the used uart available to all Rockchip platform code at all times. This includes a new rockchip_get_uart_clock as well, because while the dt-platforms right now always just default the rate defined in a constant Coreboot provides its own field for the clock rate and we don't want to loose that information for the console init. Similarly the rk_uart_* variables should move into the non-Coreboot code, to prevent them from being marked as unused, which also requires the rk_get_uart_* functions to move below the actual dt-parsing. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
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- 05 Aug, 2019 1 commit
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Heiko Stuebner authored
A previous patch already allowed to configure the uart output from the devicetree, but on Rockchip platforms we also have the issue of different vendors using different baudrates for their uarts. For example, rk3399 has a default baudrate of 115200 which is true for ChromeOS-devices and boards from Theobroma-Systems, while all the boards using the vendor boot chain actually use a baudrate of 1500000. Similarly the newly added px30 has a default of said 1500000 but some boards may want to use the more widely used 115200. The devicetree stdout-path node already contains the desired baudrate, so add simple code to parse it from there and override the default, which stays unchanged. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I7412139c3df3073a1996eb508ec08642ec6af90d
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