1. 21 Sep, 2016 6 commits
    • Yatharth Kochar's avatar
      AArch32: Add support for ARM Cortex-A32 MPCore Processor · 03a3042b
      Yatharth Kochar authored
      This patch adds ARM Cortex-A32 MPCore Processor support
      in the CPU specific operations framework. It also includes
      this support for the Base FVP port.
      
      Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d
      03a3042b
    • Yatharth Kochar's avatar
      AArch32: Support in SP_MIN to receive arguments from BL2 · d9915518
      Yatharth Kochar authored
      This patch adds support in SP_MIN to receive generic and
      platform specific arguments from BL2.
      
      The new signature is as following:
          void sp_min_early_platform_setup(void *from_bl2,
               void *plat_params_from_bl2);
      
      ARM platforms have been modified to use this support.
      
      Note: Platforms may break if using old signature.
            Default value for RESET_TO_SP_MIN is changed to 0.
      
      Change-Id: I008d4b09fd3803c7b6231587ebf02a047bdba8d0
      d9915518
    • Yatharth Kochar's avatar
      AArch32: Add ARM platform changes in BL2 · 6fe8aa2f
      Yatharth Kochar authored
      This patch adds ARM platform changes in BL2 for AArch32 state.
      It instantiates a descriptor array for ARM platforms describing
      image and entrypoint information for `SCP_BL2`, `BL32` and `BL33`.
      It also enables building of BL2 for ARCH=aarch32.
      
      Change-Id: I60dc7a284311eceba401fc789311c50ac746c51e
      6fe8aa2f
    • Yatharth Kochar's avatar
      AArch32: Add ARM platform changes in BL1 · 83fc4a93
      Yatharth Kochar authored
      This patch adds ARM platform changes in BL1 for AArch32 state.
      It also enables building of BL1 for ARCH=aarch32.
      
      Change-Id: I079be81a93d027f37b0f7d8bb474b1252bb4cf48
      83fc4a93
    • Yatharth Kochar's avatar
      AArch32: Common changes needed for BL1/BL2 · 1a0a3f06
      Yatharth Kochar authored
      This patch adds common changes to support AArch32 state in
      BL1 and BL2. Following are the changes:
      
      * Added functions for disabling MMU from Secure state.
      * Added AArch32 specific SMC function.
      * Added semihosting support.
      * Added reporting of unhandled exceptions.
      * Added uniprocessor stack support.
      * Added `el3_entrypoint_common` macro that can be
        shared by BL1 and BL32 (SP_MIN) BL stages. The
        `el3_entrypoint_common` is similar to the AArch64
        counterpart with the main difference in the assembly
        instructions and the registers that are relevant to
        AArch32 execution state.
      * Enabled `LOAD_IMAGE_V2` flag in Makefile for
        `ARCH=aarch32` and added check to make sure that
        platform has not overridden to disable it.
      
      Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
      1a0a3f06
    • Yatharth Kochar's avatar
      ARM platform changes for new version of image loading · a8aa7fec
      Yatharth Kochar authored
      This patch adds changes in ARM platform code to use new
      version of image loading.
      
      Following are the major changes:
        -Refactor the signatures for bl31_early_platform_setup()
         and arm_bl31_early_platform_setup() function to use
         `void *` instead of `bl31_params_t *`.
        -Introduce `plat_arm_bl2_handle_scp_bl2()` to handle
         loading of SCP_BL2 image from BL2.
        -Remove usage of reserve_mem() function from
         `arm_bl1_early_platform_setup()`
        -Extract BL32 & BL33 entrypoint info, from the link list
         passed by BL2, in `arm_bl31_early_platform_setup()`
        -Provides weak definitions for following platform functions:
           plat_get_bl_image_load_info
           plat_get_next_bl_params
           plat_flush_next_bl_params
           bl2_plat_handle_post_image_load
        -Instantiates a descriptor array for ARM platforms
         describing image and entrypoint information for
         `SCP_BL2`, `BL31`, `BL32` and `BL33` images.
      
      All the above changes are conditionally compiled using the
      `LOAD_IMAGE_V2` flag.
      
      Change-Id: I5e88b9785a3df1a2b2bbbb37d85b8e353ca61049
      a8aa7fec
  2. 19 Sep, 2016 1 commit
  3. 15 Sep, 2016 3 commits
    • Jeenu Viswambharan's avatar
      CSS: Implement support for NODE_HW_STATE · 3cc17aae
      Jeenu Viswambharan authored
      This patch implements CSS platform hook to support NODE_HW_STATE PSCI
      API. The platform hook queries SCP to obtain CSS power state. Power
      states returned by SCP are then converted to expected PSCI return codes.
      
      Juno's PSCI operation structure is modified to use the CSS
      implementation.
      
      Change-Id: I4a5edac0e5895dd77b51398cbd78f934831dafc0
      3cc17aae
    • Jeenu Viswambharan's avatar
      SCPI: Add function to query CSS power state · 05b128f2
      Jeenu Viswambharan authored
      This patch adds the function scpi_get_css_power_state to perform the
      'Get CSS Power State' SCP command and handle its response. The function
      parses SCP response to obtain power states of requested cluster and CPUs
      within.
      
      Change-Id: I3ea26e48dff1a139da73f6c1e0893f21accaf9f0
      05b128f2
    • Jeenu Viswambharan's avatar
      FVP: Implement support for NODE_HW_STATE · 1298ae02
      Jeenu Viswambharan authored
      This patch implements FVP platform hook to support NODE_HW_STATE PSCI
      API. The platform hook validates the given MPIDR and reads corresponding
      status from FVP power controller, and returns expected values for the
      PSCI call.
      
      Change-Id: I286c92637da11858db2c8aba8ba079389032de6d
      1298ae02
  4. 13 Sep, 2016 16 commits
  5. 12 Sep, 2016 1 commit
    • Leon Chen's avatar
      Support for Mediatek MT6795 SoC · c1ff80b1
      Leon Chen authored
      This patch support single core to boot to Linux kernel
      through Trusted Firmware.
      It also support 32 bit kernel and 64 bit kernel booting.
      c1ff80b1
  6. 09 Sep, 2016 5 commits
    • Caesar Wang's avatar
      rockchip: fixes some typo · 7e1bedb6
      Caesar Wang authored
      As the checkpatch reports the warning or error.
      
      plat/rockchip/common/plat_pm.c:96:
      ERROR: do not set execute permissions for source files
      plat/rockchip/rk3399/drivers/pmu/pmu.c:294:
      ERROR: do not set execute permissions for source files
      
      plat/rockchip/common/plat_pm.c:286: WARNING: line over 80 characters
      plat/rockchip/common/plat_pm.c:287: WARNING: line over 80 characters
      
      Change-Id: Ib347da21c56551c31df3f90f03777b13c75d5c26
      7e1bedb6
    • Caesar Wang's avatar
      rockchip: SIP call use 32 bit return value for rk3399 · a8656400
      Caesar Wang authored
      for compatible 32bit and 64bit, we use 0x82xxxxxx as function ID,
      we modify SIP call function return value to 32 bit.
      
      Change-Id: Ib99b03a9ea423853aaa296dcc634ee82c622a552
      a8656400
    • Caesar Wang's avatar
      rockchip: set gpio2 ~ gpio4 to input and pull none mode · 2bff35bb
      Caesar Wang authored
      For save power cosumption, if gpio power supply shut down, we need to
      set gpio2 ~ gpio4 to input and HiZ status when suspend, and recovery
      they status when rusume. we do it base on apio pass from loader.
      
      Change-Id: I59fd2395e5e37e63425472a39f519822c9197e4c
      2bff35bb
    • Caesar Wang's avatar
      rockchip: support disable/enable specific gpio when suspend/resume · e550c631
      Caesar Wang authored
      some specific board need to disable/enable specific gpio when
      suspend/resume, so we add this function, bootloader can pass the
      specific gpio, and we can handle these gpios in bl31 suspend/resuem
      function.
      
      Change-Id: I373b03ef9202ee4a05a2b9caacdfa01b47ee2177
      e550c631
    • Caesar Wang's avatar
      rockchip/rk3399: improve gpio driver and support get pull mode function · 536c2492
      Caesar Wang authored
      We may need gpio pull mode later, so add this function.
      Besides fix a set pull mode bug, and save gpio clock gate,
      when operate the gpio, we will enable gpio clock, when
      finish gpio operate, restore gpio clock gate status.
      
      Change-Id: Ia1d602804f571a17f5ddc499908663b968b02974
      536c2492
  7. 08 Sep, 2016 1 commit
    • Tony Xie's avatar
      rockchip: fix the scu idle for rk3399 · 63ebf051
      Tony Xie authored
      As rk3399 reported the d8/octane scores drop 10% with cpu idle.
      The root cause is thc cpu cluster enter the slow mode.
      We don't need switch the clock to 24MHz if cpu cluster enter the
      retention mode. In order to improve performance, it just needs for
      cluster enter powering off mode.
      
      Also, we shouldn't do anything for hlvl if the system is off.
      
      Change-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119
      63ebf051
  8. 25 Aug, 2016 5 commits
  9. 24 Aug, 2016 1 commit
    • Caesar Wang's avatar
      rockchip: on rk3399 init the PMU counts at boot; set 24M/32k properly · 0786d688
      Caesar Wang authored
      In a previous change we mistakenly thought that PMU_24M_EN_CFG directly
      controlled whether the PMU counts ran off the 32k vs. 24M clock.
      Apparently that's not true.  Real logic is now documented in code.
      
      Also in the previous change we mistaknely though that PMU_24M_EN_CFG was
      normally supposed to be 1 and we should "restore" it at resume time.
      This is a terrible idea and made the system totally unreliable after
      resume.  Apparently PMU_24M_EN_CFG should always be 0 with all the
      current code and settings.
      
      Let's fix the above two problems.  While we're changing all of this,
      let's also:
      
      1. Init at boot time.  Many of these counts are used when the system is
         running normally.  We want the behavior at boot to match the behavior
         after suspend/resume.
      
      2. Init CPU counts to be 1 us.  Although old code was trying to set this
         to 1 ms (1000x slower) at suspend/resume time, we've been testing the
         kernel with 1 us for a long time now.  That's because the kernel (at
         boot time) set these values to 24.  Let's keep at 24 until we know
         that's wrong.
      
      3. Init GPU counts to be 1 us.  Old code wasn't touching the GPU, but as
         documented in comments it makes sense to init here.  Do it.
      
      4. Document the crap out of this code, since the SoC's behavior is
         confusing and poorly documented in the TRM.
      
      5. Increase some stabilization times to 30 ms (from 3 ms).  It's unclear
         that a full 30 ms is needed, but let's be safe for now.
      
      This also inits the counts for the GPU.
      
      (Thanks to Doug's patch that come from https://crosreview.com/372381)
      
      Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22
      0786d688
  10. 19 Aug, 2016 1 commit
    • Sandrine Bailleux's avatar
      Add WFI in platform's unexpected error handlers · 8c9e1af0
      Sandrine Bailleux authored
      This patch adds a WFI instruction in the default implementations of
      plat_error_handler() and plat_panic_handler(). This potentially reduces
      power consumption by allowing the hardware to enter a low-power state.
      The same change has been made to the FVP and Juno platform ports.
      
      Change-Id: Ia4e6e1e5bf1ed42efbba7d0ebbad7be8d5f9f173
      8c9e1af0