- 12 Oct, 2020 2 commits
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Lionel Debieve authored
Chip select is retrieved from device tree and check must be done regarding the MAX_CS defined. Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Reviewed-by:
Christophe KERELLO <christophe.kerello@st.com> Change-Id: I03144b133bd51a845a4794f0f6bbd9402fc04936
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Christophe Kerello authored
FMC node bindings are modified to add EBI controller node. FMC driver and associated device tree files are modified to support these new bindings. Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc Signed-off-by:
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- 08 Oct, 2020 1 commit
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Lionel Debieve authored
Clear interrupt flag register after each sector read to avoid issue when checking the register status. Without clearing the interrupt, the status read doesn't wait properly the ready bit. Signed-off-by:
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- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by:Etienne Carriere <etienne.carriere@st.com>
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- 23 Mar, 2020 1 commit
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Yann Gautier authored
The variable is wrongly set to 0L, whereas it is an unsigned int, it should then be 0U. Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238 Signed-off-by:Yann Gautier <yann.gautier@st.com>
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- 20 Jan, 2020 1 commit
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Lionel Debieve authored
Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by:
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