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  1. 29 Jul, 2020 1 commit
  3. 27 Jul, 2020 1 commit
  5. 21 Jul, 2020 2 commits
  7. 20 Jul, 2020 1 commit
    • Alexei Fedorov's avatar
      TF-A GICv2 driver: Introduce makefile · 1322dc94
      Alexei Fedorov authored 
      

This patch moves all GICv2 driver files into new added
'gicv2.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.

NOTE: Usage of 'drivers/arm/gic/common/gic_common.c' file
is now deprecated and platforms with GICv2 driver need to
be modified to include 'drivers/arm/gic/v2/gicv2.mk' in
their makefiles.

Change-Id: Ib10e71bdda0e5c7e80a049ddce2de1dd839602d1
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      1322dc94
  9. 16 Jul, 2020 1 commit
    • johpow01's avatar
      IO Driver Misra Cleanup · d471bd9c
      johpow01 authored 
      

This patch cleans up MISRA C violations in the IO driver files.  Some
things did not make sense to fix or would require sweeping changes
but the simple issues have been resolved.

Defects Fixed

File                        Line Rule
drivers/io/io_fip.c         39   MISRA C-2012 Rule 5.6 (required)
drivers/io/io_fip.c         52   MISRA C-2012 Rule 8.9 (advisory)
drivers/io/io_fip.c         60   MISRA C-2012 Rule 5.9 (advisory)
drivers/io/io_fip.c         285  MISRA C-2012 Rule 8.9 (advisory)
drivers/io/io_fip.c         336  MISRA C-2012 Rule 15.4 (advisory)
drivers/io/io_fip.c         340  MISRA C-2012 Rule 15.4 (advisory)
drivers/io/io_fip.c         342  MISRA C-2012 Rule 15.4 (advisory)
drivers/io/io_memmap.c      30   MISRA C-2012 Rule 5.6 (required)
drivers/io/io_memmap.c      32   MISRA C-2012 Rule 5.9 (advisory)
drivers/io/io_memmap.c      85   MISRA C-2012 Rule 11.8 (required)
drivers/io/io_semihosting.c 66   MISRA C-2012 Rule 11.8 (required)
drivers/io/io_storage.c     73   MISRA C-2012 Rule 5.9 (advisory)
drivers/io/io_storage.c     116  MISRA C-2012 Rule 13.4 (advisory)
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: Id9b1b2b684588d4eaab674ed4ed04f3950dd21f4
      d471bd9c
  11. 13 Jul, 2020 1 commit
  13. 11 Jul, 2020 1 commit
  15. 10 Jul, 2020 5 commits
  17. 09 Jul, 2020 1 commit
  19. 08 Jul, 2020 5 commits
  21. 07 Jul, 2020 1 commit
    • Varun Wadekar's avatar
      drivers: arm: gicv3: auto-detect presence of GIC600-AE · 8e570b71
      Varun Wadekar authored 
      

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC600 interrupt controller to function with the generic GIC driver.

Verified with tftf-validation test suite

******************************* Summary *******************************
> Test suite 'Framework Validation'
                                                                Passed
> Test suite 'Timer framework Validation'
                                                                Passed
=================================
Tests Skipped : 0
Tests Passed  : 6
Tests Failed  : 0
Tests Crashed : 0
Total tests   : 6
=================================
NOTICE:  Exiting tests.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574
      8e570b71
  23. 24 Jun, 2020 2 commits
  25. 22 Jun, 2020 1 commit
    • Sandeep Tripathy's avatar
      TF-A GIC driver: Add barrier before eoi · 5eb16c47
      Sandeep Tripathy authored 
      

It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occurred.

A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.

GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.

GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.

Hence a dsb can ensure from core no writes are issued before the previous
writes are *complete*.
Signed-off-by: default avatarSandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: Ie6362009e2f91955be99dca8ece14ade7b4811d6
      5eb16c47
  27. 19 Jun, 2020 5 commits
  29. 17 Jun, 2020 4 commits
  31. 15 Jun, 2020 1 commit
    • Manish Pandey's avatar
      tbbr: add chain of trust for Secure Partitions · 68758dd6
      Manish Pandey authored 
      with sha 44f1aa8e

, support for Silicon Provider(SiP) owned Secure
Partition(SP) was added for dualroot CoT. This patch extends this
support for tbbr CoT.

Earlier tbbr CoT for SPs was left to avoid adding new image types in
TBBR which could possibly be seen as deviation from specification.
But with further discussions it is understood that TBBR being a
*minimal* set of requirements that can be extended as long as we don't
violate any of the musts, which is the case with adding SP support.
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: I1b9e3ebdd7d653f1fd4cc3bd910a69871b55ecbb
      68758dd6
  33. 09 Jun, 2020 2 commits
    • Andre Przywara's avatar
      GICv3: GIC-600: Detect GIC-600 at runtime · b4ad365a
      Andre Przywara authored 
      

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b4ad365a
    • Manish Pandey's avatar
      dualroot: add chain of trust for secure partitions · 44f1aa8e
      Manish Pandey authored 
      

A new certificate "sip-sp-cert" has been added for Silicon Provider(SiP)
owned Secure Partitions(SP). A similar support for Platform owned SP can
be added in future. The certificate is also protected against anti-
rollback using the trusted Non-Volatile counter.

To avoid deviating from TBBR spec, support for SP CoT is only provided
in dualroot.
Secure Partition content certificate is assigned image ID 31 and SP
images follows after it.

The CoT for secure partition look like below.
+------------------+       +-------------------+
| ROTPK/ROTPK Hash |------>| Trusted Key       |
+------------------+       | Certificate       |
                           | (Auth Image)      |
                          /+-------------------+
                         /                   |
                        /                    |
                       /                     |
                      /                      |
                     L                       v
+------------------+       +-------------------+
| Trusted World    |------>| SiP owned SPs     |
| Public Key       |       | Content Cert      |
+------------------+       | (Auth Image)      |
                        /   +-------------------+
                       /                      |
                      /                      v|
+------------------+ L     +-------------------+
| SP_PKG1 Hash     |------>| SP_PKG1           |
|                  |       | (Data Image)      |
+------------------+       +-------------------+
        .                           .
        .                           .
        .                           .
+------------------+       +-------------------+
| SP_PKG8 Hash     |------>| SP_PKG8           |
|                  |       | (Data Image)      |
+------------------+       +-------------------+
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ia31546bac1327a3e0b5d37e8b99c808442d5e53f
      44f1aa8e
  35. 06 Jun, 2020 5 commits