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This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization
routine. Setting up the AIPSTZ controller is required to inform the SoC
interconnect fabric which bus-masters can read/write and if the read/writes
are buffered.

For our purposes the initial configuration is for everything to be open. We
can lock-down later on as necessary.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch defines:

- The full range of IO-mux register offsets relative to the base address of
  the IO-mux block base address.

- The bits for muxing the UART1 TX/RX lines.

- The bits for muxing the UART6 TX/RX lines.

- The pad control pad bits for the UART

Two functions are provided to configure pad muxes:

- void io_muxc_set_pad_alt_function(pad_mux_offset, alt_function)
  Takes a pad_mux_offset and sets the alt_function bit-mask supplied.
  This will have the effect of switching the pad into one of its defined
  peripheral functions. These peripheral function modes are defined in the
  NXP documentation and need to be referred to in order to correctly
  configure a new alternative-function.

- void io_muxc_set_pad_features(pad_feature_offset, pad_features)
  Takes a pad_feature_offset and applies a pad_features bit-mask to the
  indicated pad.
  This function allows the setting of PAD drive-strength, pull-up values,
  hysteresis glitch filters and slew-rate settings.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch initializes USB core clocks for the i.MX7.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch initializes the watchdog clocks for the i.MX7.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch adds an internal UART init routine that gets called from the
external facing clock init function.

In the first pass this call does an explicit disable of all UART
clock-gates. Later changes will enable only the UART clock-gates we care
about.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This set of patches adds a very minimal layer of USB enabling patches to
clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs,
the main USB clock etc, not to different instances of the same IP block.

As a result this patch-set takes the clock CCGR clock identifier directly
rather than as an index of an instance of blocks of the same type.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch adds a set of functions to enable the clock for each of the
watchdog IP blocks.

Unlike the MMC and UART blocks, the watchdog blocks operate off of the one
root clock, only the clock-gates are enable/disabled individually.

As a consequence the function clock_set_wdog_clk_root_bits() is used to set
the root-slice just once for all of the watchdog blocks.

Future implementations may need to change this model but for now on the one
supported processor and similar NXP SoCs this model should work fine.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This commit:

- Defines a clock stub with a conjoined header defining the clock
  memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
  register set to read, set, clear and toggle individual clock gates into
  one of four states based bitmask.

  00: Domain clocks not needed
  01: Domain clocks needed when in RUN
  10: Domain clocks needed when in RUN and WAIT
  11: Domain clocks needed all the time

- Defines clock control register bits

  There are various quadrumvirate register blocks target-root, misc-root,
  post-root, pre-root in the CCM.

  The number of registers is huge but the four registers in each
  quadrumvirate block contain the same bits, so the number of bit
  definitions is actually quite low.

- Defines clock identifiers

  An array of clock gates is provided in the CCM block. In order to index
  that array and thus enable/disable clock gates for the right components,
  we need to provide meaningful names to the indices.

  Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
  Rev 0.1 provides the relevant details.

- Defines target mux select bits
  This is a comprehensive definition of the target clock mux select bits.
  These bits are required to correctly select the clock source. Defining
  all of the bits up-front even for unused blocks in ATF means we can
  switch on any block we want at a later date without having to write new
  code in the clock-mux layer.

- Defines identifier indices into root-slice array
  The root-slice array of control registers has a specific set of indices,
  which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
  Provides a clock-gate enable/disable routine via the set/clr
  registers in a given clock-gate control register block.

  This index passed should be one of the enums associated with CCM and
  depending on enable/disable being passed either set or clr will be
  written to.

  The Domain0 bits are currently the only bits targeted by this write, more
  work may need to be done on the domain bits in subsequent patches as a
  result.

- imx: Adds set/clr routines to clock layer

  Adds a set and clr routine to the clock layer. These routines allow us to
  access the set and clear registers of the "target" block registers. These
  are the registers where we select the clock source from the available list.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we frequently need
to map compatible blocks to different addresses depending on the SOC.

This patch adds a basic memory map of the i.MX7 based on the "Cortex-A7
Memory Map" section 2.12 of "i.MX7Solo Applications Processor Reference
Manual, Rev 0.1 08/2016"

In memory map terms the i.MX7S and i.MX7D are identical with the D
variant containing two Cortex-A7 cores plus a Cortex-M core and the S
variant containing one Cortex-A7 and one Cortex-M.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add USDHC driver to support boot EMMC. Only initialization
and single/multiple block read are tested.

[bod: fixed checkpatch.pl complaints]
[bod: changed name to imx_usdhc for namespace consistency]
[bod: squashed antecedent fixes into this one patch]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add missing response type for SWITCH command and STOP_TRANSMISSION
so that controller can be configured accordingly.

[bod: ported this change from Jun's eMMC patches to the MMC driver]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

The R3 response type definition should be (1 << 0). Make sure we define the
expected response code in the appropriate fashion.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add response flag into ID definition so that driver does not
need to handle it again.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Add delay timer API so that it can be called by delay timer
layer and used as delay timer globally.

[bod: changed name from imx_delay_timer -> imx_gpt ]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

This patch does two main things

- It implements the crash console UART init in assembly, as a
  hard-coded 115200 8N1 assumed from the 24 MHz clock.

  If the clock setup code has not run yet, this code can't work but,
  setting up clocks and clock-gates is way out of scope for this type of
  recovery function.

- It adds code to write a character out of the NXP UART without using any
  stack-based operations when doing so.

- Provides support for crash console in DCE or DTE mode.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

- Adds a simple register read/write abstraction to cut-down on the
  amount of typing and text required to access UART registers in this driver.

- Adds a console getc() callback.

- Adds a console putc() callback, translating '\n' to '\r' + '\n'.

- Initializes the MXC UART, take a crude method of calculating the
  BAUD rate generator. The UART clock-gates must have been enabled prior
  to launching the UART init code.
  Special care needs to be taken to ensure the UBIR is initialized before the
  UBMR and we need to ensure that UCR2.SRST comes good before trying to
  program other registers associated with the UART.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Fix some MISRA defect in log helpers

No functional changes.

Change-Id: I850f08718abb69d5d58856b0e3de036266d8c2f4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

No functional changes.

Change-Id: I907aa47565af2a6c435a5560041fd2b59e65c25c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Some MISRA fixes in BL31, cci and smmu

context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation

MISRA fixes for the GIC driver

Introduce backtrace function

Change-Id: Ifdb0ceec19d267b14d796b5d31f08f7342190484
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I2954a99d5b72069bcb7bac9d6926c6209d6ba881
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I8fbb4c785e7e07c7241e0c399a9b65161985c9df
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I130e35d55c474ecd80f9a825be23620d5bc1a715
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I11509a3271d7608048d49e7dd5192be0c2a313f0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I08447b44fffb6e54f9fab957eee369ccbda4247a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I945029ca26ea2e63f0d92c5f33019b882f23bd72
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: Ib587f12f36810fc7d4f4b8f575195554299b8ed4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

When any of these functions is called the backtrace will be printed to
the console.

Change-Id: Id60842df824b320c485a9323ed6b80600f4ebe35
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This function diplays the backtrace, the current EL and security state
to allow a post-processing tool to choose the right binary to interpret
the dump.

The output can be fed to GNU addr2line to resolve function names given
an ELF binary compiled with debug information. The "-i" flag is
recommended to improve display in case of inlined functions. The *.dump
files generated during the build process can also be used.

The function works in AArch64 and AArch32. In AArch32 it only works in
A32 mode (without T32 interworking), which is enforced in the Makefile.

Sample output of a backtrace at EL3:

    BACKTRACE: START: function_name
    0: EL3: 0x798
    1: EL3: 0x538
    2: EL3: 0x550
    3: EL3: 0x55c
    4: EL3: 0x568
    5: EL3: 0x5a8
    6: EL3: 0xf4
    BACKTRACE: END: function_name

In order to enable it the new option ENABLE_BACKTRACE must be set to 1.
This option is set to 1 by default only in AArch64 debug builds. As
usual, it can be overridden by the platform makefile and in the build
command line.

Change-Id: Icaff39b0e5188329728be2f3c72b868b2368e794
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

At the moment the AArch32 instruction set isn't specified in the command
line, which means that the compiler is free to choose the one it sees
fit. This decision may change between compiler versions, so it is better
to specify it manually.

The build option AARCH32_INSTRUCTION_SET has been introduced for this
reason. This option can be set to T32 or A32 to pass the correct flags
to the compiler.

The current behaviour is to default to T32 due to it's smaller size.

Change-Id: I02297eb1d9404b5868ff7c054fbff9b3cda7fdb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

maintainers: Update maintainer for sgi/sgm platforms

K3 PSCI Support