- 07 Dec, 2020 8 commits
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G.Pangao authored
1.Modify this driver to make it more complete and more standard. 2.And makes this driver available for more IC services. 3.Solve some bugs in the software. Signed-off-by: G.Pangao <gtk_pangao@mediatek.com> Change-Id: I284956d47ebbbd550ec93767679181185e442348
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Hsin-Hsiung Wang authored
add power-off support Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: If19e99971515a8ae1ac9ae21046e4382adc18a69
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Hsin-Hsiung Wang authored
add pmic mt6359p driver Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I20f2218f7d2087e8d2bf31258cf92a02e0dab77d
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Nina Wu authored
Init delay_timer for the use of delay functions Change-Id: I35aefd7515bb9259634c8b6bc37d8c74da96e8f1 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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Dehui Sun authored
Enable NS access for all systimers. Signed-off-by: Dehui Sun <dehui.sun@mediatek.com> Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a
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James Liao authored
Implement PSCI platform OPs to support CPU hotplug and MCDI. Change-Id: I31abfc752b69ac40e70bc9e7a55163eb39776c44 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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James Liao authored
Add MCDI related drivers to handle CPU powered on/off in CPU suspend. Change-Id: I5110461e8eef86f8383b45f197ec5cb10dbfeb3e Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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James Liao authored
Add SPMC driver for CPU power on/off. Change-Id: I526b98d5885855efce019dd09cfd93b8816cbf19 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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- 28 Oct, 2020 3 commits
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Dehui Sun authored
add timer driver. Signed-off-by: Dehui Sun <dehui.sun@mediatek.com> Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7
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Nina Wu authored
Add system_reset function in psci ops Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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gtk_pangao authored
1.add sys_cirq driver 2.add gic api for cirq Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
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- 26 Oct, 2020 1 commit
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Po Xu authored
add GPIO driver Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd Signed-off-by: Po Xu <jg_poxu@mediatek.com>
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- 21 Oct, 2020 1 commit
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Fengquan Chen authored
add timer driver. Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com> Change-Id: I60a7273f922233a618a6163b802c0858ed89f75f
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- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 25 Sep, 2020 1 commit
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Greta Zhang authored
1. Implement GIC600 driver support and init 2. Remove unused debug info Signed-off-by: Greta Zhang <greta.zhang@mediatek.com> Change-Id: I30c08c531e705debc029071e4e970048e261c386
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- 01 Sep, 2020 1 commit
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Hsin-Yi Wang authored
Add jedec info for mt8173, mt8183, and mt8192. [1] http://www.softnology.biz/pdf/JEP106AV.pdf Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Change-Id: Iab36fd580131f0b09b27223fba0e9d1e187d9196
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- 31 Jul, 2020 1 commit
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Nina Wu authored
- Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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- 25 Apr, 2020 1 commit
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Masahiro Yamada authored
Move the data section to the common header. I slightly tweaked some scripts as follows: [1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, which is 1 by default, but overridden by bl1.ld.S. Currently, ALIGN(16) of the .data section is redundant because commit 41286590 ("Fix boot failures on some builds linked with ld.lld.") padded out the previous section to work around the issue of LLD version <= 10.0. This will be fixed in the future release of LLVM, so I am keeping the proper way to align LMA. [2] bl1.ld.S and bl2_el3.ld.S define __DATA_RAM_{START,END}__ instead of __DATA_{START,END}__. I put them out of the .data section. [3] SORT_BY_ALIGNMENT() is missing tsp.ld.S, sp_min.ld.S, and mediatek/mt6795/bl31.ld.S. This commit adds SORT_BY_ALIGNMENT() for all images, so the symbol order in those three will change, but I do not think it is a big deal. Change-Id: I215bb23c319f045cd88e6f4e8ee2518c67f03692 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 24 Apr, 2020 1 commit
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Masahiro Yamada authored
The stacks section is the same for all BL linker scripts. Move it to the common header file. Change-Id: Ibd253488667ab4f69702d56ff9e9929376704f6c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 02 Apr, 2020 3 commits
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Masahiro Yamada authored
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL and PMF_TIMESTAMP, which previously existed only in BL31. This is not a big deal because unused data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts. I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition. The bss section has bigger alignment. I added BSS_ALIGN for this. Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this change, the BSS symbols in SP_MIN will be sorted by the alignment. This is not a big deal (or, even better in terms of the image size). Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The common section data are repeated in many linker scripts (often twice in each script to support SEPARATE_CODE_AND_RODATA). When you add a new read-only data section, you end up with touching lots of places. After this commit, you will only need to touch bl_common.ld.h when you add a new section to RODATA_COMMON. Replace a series of RO section with RODATA_COMMON, which contains 6 sections, some of which did not exist before. This is not a big deal because unneeded data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts. When I was working on this commit, the BL1 image size increased due to the fconf_populator. Commit c452ba15 ("fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue. I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition. Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
These are mostly used to collect data from special structure, and repeated in many linker scripts. To differentiate the alignment size between aarch32/aarch64, I added a new macro STRUCT_ALIGN. While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional. As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE* are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array data are not populated. Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 30 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 11 Mar, 2020 1 commit
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Masahiro Yamada authored
TF-A has so many linker scripts, at least one linker script for each BL image, and some platforms have their own ones. They duplicate quite similar code (and comments). When we add some changes to linker scripts, we end up with touching so many files. This is not nice in the maintainability perspective. When you look at Linux kernel, the common code is macrofied in include/asm-generic/vmlinux.lds.h, which is included from each arch linker script, arch/*/kernel/vmlinux.lds.S TF-A can follow this approach. Let's factor out the common code into include/common/bl_common.ld.h As a start point, this commit factors out the xlat_table section. Change-Id: Ifa369e9b48e8e12702535d721cc2a16d12397895 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 10 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 25 Feb, 2020 1 commit
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 24 Feb, 2020 1 commit
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Julius Werner authored
This patch adds support for a new SMC that can be used to control the watchdog. This allows for a cleaner separation of responsibilities where all watchdog operations have to go through Trusted Firmware and we could no longer have kernel and firmware poking concurrently at the same register block. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Evan Benn <evanbenn@chromium.org> Change-Id: I4844a3559d5c956a53a74a61dd5bc2956f0cce7b
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- 14 Feb, 2020 1 commit
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Xi Chen authored
The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM), and that emi_mpu_set_region_protection will translate to the physical memory space (0-8GB). 8GB is 33-bit (the memory bus width is 33-bit on this platform), so 0x23FFFFFFFUL-EMI_PHY_OFFSET = 0x1_FFFF_FFFF. Change-Id: I7be4759ed7546f7e15a5868b6f08988928c34075 Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
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- 28 Jan, 2020 1 commit
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Louis Mayencourt authored
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iee98ded027c049d9f12d4bb5888c0496b3251b4e
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 26 Dec, 2019 1 commit
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Roger Lu authored
spm resume will restore Vmodem/Vcore voltages back based on the SPM_DVS_LEVEL. Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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- 25 Nov, 2019 2 commits
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James Liao authored
CPU0 is default on, so it doesn't need to run pwr_domain_on() at boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may encounter race condition with other CPUs. Now AARCH64 will be set with cluster on in pwr_domain_on(), and all CPUs on this cluster will be set together. It doesn't need to set AARCH64 again in pwr_domain_suspend(), so the race condition can be avoided. Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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kenny liang authored
Implement rdist save/resore functions to support low power scenarios. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7
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- 19 Nov, 2019 1 commit
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Justin Chadwell authored
Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 05 Nov, 2019 1 commit
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Roger Lu authored
1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM 2. Switch CLKSQ1/TDCLKSQ control to SPM 3. Switch ck_off/axi_26m control to SPM BUG=b:136980838 TEST=system suspend/resume passed Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18 Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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- 03 Oct, 2019 2 commits
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kenny liang authored
Add EMI MPU driver for DRAM protection. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96
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kenny liang authored
Add DEVAPC driver to control protection. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02eabbb9d26
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- 16 Sep, 2019 2 commits
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kenny liang authored
Add MCDI driver for power saving. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I93ecff4d7581f678be09dd8fb5dfaaccd5f2c22c
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kenny liang authored
Add MTK SSPM driver. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I30dd9a95456b8c3c8d18fd22120824eec97634ee
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