- 31 Jan, 2020 2 commits
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Varun Wadekar authored
This patch fixes violations of the following MISRA rules * Rule 8.5 "An external object or function shall be declared once in one and only one file" * Rule 10.3 "The value of an expression shall not be assigned to an object with a narrower essential type or of a different esential type category" Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch fixes violations for the following MISRA rules * Rule 8.4 "A compatible declaration shall be visible when an object or function with external linkage is defined" * Rule 10.1 "Operands shall not be of an inappropriate essential type" * Rule 10.6 "Both operands of an operator in which the usual arithmetic conversions are perdormed shall have the same essential type category" * Rule 17.7 "The value returned by a function having non-void return type shall be used" Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 23 Jan, 2020 3 commits
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Varun Wadekar authored
This patch removes unused functions from the NVG driver. * nvg_enable_power_perf_mode * nvg_disable_power_perf_mode * nvg_enable_power_saver_modes * nvg_disable_power_saver_modes * nvg_roc_clean_cache * nvg_roc_flush_cache Change-Id: I0387a40dec35686deaad623a8350de89acfe9393 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch updates the NVG interface header file to v6.6. Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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steven kao authored
This patch adds support to toggle SE clock, using the bpmp_ipc interface, to enable SE context save/restore. The SE sequence mostly gets called during System Suspend/Resume. Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7 Signed-off-by: steven kao <skao@nvidia.com>
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- 17 Jan, 2020 2 commits
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Vignesh Radhakrishnan authored
This patch adds support for shutdown/reboot handlers to the MCE driver. ATF communicates with mce using nvg interface for shutdown & reboot. Both shutdown and reboot use the same nvg index. However, the 1st bit of the nvg data argument differentiates whether its a shutdown or reboot. Change-Id: Id2d1b0c4fec55abf69b7f8adb65ca70bfa920e73 Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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Steven Kao authored
This patch adds a new configuration option to the platform makefiles that disables/enables strict checking mode. The config is enabled by default. Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb Signed-off-by: Steven Kao <skao@nvidia.com>
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- 12 Jan, 2020 1 commit
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Varun Wadekar authored
This patch fixes the violations of Rule 21.1 from all the header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I12e17a5d7158defd33b03416daab3049749905fc
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- 09 Jan, 2020 2 commits
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Olivier Deprez authored
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 08 Jan, 2020 1 commit
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Varun Wadekar authored
The MCE driver's helper functions were using postive values as error codes. This patch updates the functions to return negative values as error codes instead. Some functions are updated to use the right error code. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6
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- 28 Nov, 2019 13 commits
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Steven Kao authored
This patch updates the header, t194_nvg.h, to v6.4. This gets it in synch with MTS pre-release 2 - cl39748439. Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7 Signed-off-by: Steven Kao <skao@nvidia.com>
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Dilan Lee authored
"Strict checking" is a mode where secure world can access secure-only areas unlike legacy mode where secure world could access non-secure spaces as well. Secure-only areas are defined as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set. This mode not only helps prevent issues with IO-Coherency but aids with security as well. This patch implements the programming sequence required to enable strict checking mode for Tegra194 SoCs. Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0 Signed-off-by: Dilan Lee <dilee@nvidia.com>
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Varun Wadekar authored
The MCE driver checks the NVG interface version during boot and disaplys the hardware and software versions on the console. The software version is being displayed as zero. This patch updates the prints to use the real NVG header version instead. Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Vignesh Radhakrishnan authored
This patch does the following: - cstate_info variable is used to pass on requested cstate to mce - Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info - cg_cstate values can range from 0 to 7, with 7 representing cg7 - Thus, cg_cstate is to be encoded using 3 bits (val: 0-7) - Fix this, as per ISS and ensure bits 8, 9, 10 are used Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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Steven Kao authored
This patch adds the driver, to implement the programming sequence to save/restore hardware context, during System Suspend/Resume. Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Jeff Tsai <jefft@nvidia.com>
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Anthony Zhou authored
Rule 8.4, A compatible declaration shall be visible when an object or function with external linkage is defined. Add function delaration to the header file. Add suffix U to the unsigned constant define. Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch cleans up the mce driver files to remove all the unsupported functionality. The MCE/NVG interface is not restricted to the EL3 space, so clients can issue commands to the MCE firmware directly. Change-Id: Idcebc42f31805f9c1abe1c1edc17850151aca11d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Fix variable essential type doesn't match [Rule 10.3] Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Steven Kao authored
This patch updates t194_nvg.h to v6.1 and does not issue NVG commands for unsupported platforms. Change-Id: I506b594a70a3651d01a412ab79b3c8919b1d66f1 Signed-off-by: Steven Kao <skao@nvidia.com>
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Steven Kao authored
This patch updates the cache ops to use system registers in order to trigger cache flush/clean operations. Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0 Signed-off-by: Steven Kao <skao@nvidia.com>
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Krishna Sitaraman authored
This patch adds proper checks for the cpu c-stats. It checks both cpu id and stat id before sending the nvg request to ccplex. Change-Id: I732957d1e10d6ce6cffb2c6f5963ca614aadd948 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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Steven Kao authored
This patch changes direct writes to ACTLR_ELx registers to use read-modify-write instead. Change-Id: I536dce75c01356ce054dd2edee80875e56164439 Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
This patch adds platform support for the Memory Controller and SMMU drivers, for the Tegra194 SoC. Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 13 Nov, 2019 1 commit
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Anthony Zhou authored
To fix MISRA defects, remove union in t186 MCE drivers this driver should compatible with that. Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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- 24 Oct, 2019 6 commits
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Rohit Khanna authored
Dont run MCE firmware on pre-silicon emulation platforms Change-Id: I2a8d653e46f494621580ca92271a18e62f648859 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
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Pritesh Raithatha authored
GPU, MPCORE and PTC clients are changed and not going through SMMU. Removing it from streamid list. Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Steven Kao authored
This patch enable MCE driver for T19x SoC. The MCE driver takes care of the communication with the MCE firmware to achieve: - Cold boot - Warm boot - Core/Cluster/System Power management - Custom MCE requests Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d Signed-off-by: Steven Kao <skao@nvidia.com>
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Pritesh Raithatha authored
This patch adds support for all three SMMU devices present on the SoC. The following changes have been done: Add SMMU devices to the memory map Update register read and write functions Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Pritesh Raithatha authored
Define mc sid and txn override regs and sec cfgs. Create array for mc sid override regs and sec config that is used to initialize mc. Add smmu ctx regs array to hold register values during suspend. Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Varun Wadekar authored
This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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