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  1. 19 Mar, 2021 1 commit
  3. 16 Mar, 2021 1 commit
  5. 15 Mar, 2021 1 commit
    • Olivier Deprez's avatar
      SPM: declare third cactus instance as UP SP · e96fc8e7
      Olivier Deprez authored 
      

The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: default avatarOlivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
      e96fc8e7
  7. 10 Mar, 2021 1 commit
  9. 09 Mar, 2021 1 commit
  11. 08 Mar, 2021 1 commit
  13. 03 Mar, 2021 6 commits
  15. 02 Mar, 2021 1 commit
  17. 01 Mar, 2021 3 commits
  19. 25 Feb, 2021 2 commits
  21. 24 Feb, 2021 2 commits
  23. 17 Feb, 2021 1 commit
  25. 16 Feb, 2021 1 commit
  27. 15 Feb, 2021 1 commit
    • Andre Przywara's avatar
      plat/arm: juno: Condition Juno entropy source with CRC instructions · eb18ce32
      Andre Przywara authored 
      

The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.

To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.

This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.

Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      eb18ce32
  29. 12 Feb, 2021 1 commit
    • Pankaj Gupta's avatar
      nxp: added the makefile helper macros · b749ae3d
      Pankaj Gupta authored 
      

NXP specifc macro SET_NXP_MAKE_FLAG is added.

NXP has pool of multiple IPs. This macro helps:
- In soc.mk, this macro help the selected IP source files to be included
  for that SoC.
  -- The set of IPs required for one NXP SoC is different to the set of IPs
     required by another NXP SoC.

- For the same SoC,
  -- For one feature, the IP may be required in both BL2 and BL31.
  -- Without the above feature, that IP may be required in one.
     This macro help in selecting the inclusion of source and header files to:
     --- BL2 only
     --- BL31 only
     --- COMM (used by BL2 and BL31)
Signed-off-by: default avatarPankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cdb13b89aa815fc5219cf8bfb9666d0a9f78765
      b749ae3d
  31. 11 Feb, 2021 4 commits
  33. 09 Feb, 2021 4 commits
    • Manish V Badarkhe's avatar
      plat/arm: fvp: Protect GICR frames for fused/unused cores · f98630fb
      Manish V Badarkhe authored 
      

Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.

This opens up the security hole where the active core can write
the GICR frame of fused/inactive core. To avoid this issue, disable
the GICR frame of all inactive cores as below:

1. After primary CPU boots up, map GICR region of all cores as
   read-only.
2. After primary CPU boots up, map its GICR region as read-write
   and initialize its redistributor interface.
3. After secondary CPU boots up, map its GICR region as read-write
   and initialize its redistributor interface.
4. All unused/fused core's redistributor regions remain read-only and
   write attempt to such protected regions results in an exception.

As mentioned above, this patch offers only the GICR memory-mapped
region protection considering there is no facility at the GIC IP
level to avoid writing the redistributor area.

These changes are currently done in BL31 of Arm FVP and guarded under
the flag 'FVP_GICR_REGION_PROTECTION'.

As of now, this patch is tested manually as below:
1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core.
2. Verify data abort triggered by manually updating the ‘GICR_CTLR’
   register of core 1’s(fused) redistributor from core 0(active).

Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      f98630fb
    • Manish V Badarkhe's avatar
      plat/arm: fvp: Do not map GIC region in BL1 and BL2 · e0cea783
      Manish V Badarkhe authored 
      

GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memory regions in the
future.

Retains mapping of CCN interconnect region in BL1 and BL2
overlapped with the GIC memory region.

Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      e0cea783
    • Andre Przywara's avatar
      plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31 · e27340a7
      Andre Przywara authored 
      

So far the ARM platform Makefile would require that RESET_TO_BL31 is set
when we ask for the ARM_LINUX_KERNEL_AS_BL33 feature.
There is no real technical reason for that, and the one place in the
code where this was needed has been fixed.

Remove the requirement of those two options to be always enabled
together.
This enables the direct kernel boot feature for the Foundation FVP
(as described in the documentation), which requires a BL1/FIP
combination to boot, so cannot use RESET_TO_BL31.

Change-Id: I6814797b6431b6614d684bab3c5830bfd9481851
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      e27340a7
    • Andre Przywara's avatar
      plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33 · c99b8c89
      Andre Przywara authored 
      

At the moment we have the somewhat artifical limitation of
ARM_LINUX_KERNEL_AS_BL33 only being used together with RESET_TO_BL31.

However there does not seem to be a good technical reason for that,
it was probably just to differentate between two different boot flows.

Move the initial register setup for ARM_LINUX_KERNEL_AS_BL33 out of the
RESET_TO_BL31 #ifdef, so that we initialise the registers in any case.

This allows to use a preloaded kernel image when using BL1 and FIP.

Change-Id: I832df272d3829f077661f4ee6d3dd9a276a0118f
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      c99b8c89
  35. 08 Feb, 2021 1 commit
  37. 05 Feb, 2021 1 commit
  39. 04 Feb, 2021 1 commit
  41. 03 Feb, 2021 2 commits
    • Julius Werner's avatar
      qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument · de67080f
      Julius Werner authored 
      

The NUM_APID value was derived from kernel device tree sources, but I
made a conversion mistake: the amount of bytes in the APID map is the
total size of the "core" register range (0x1100) minus the offset of the
APID map in that range (0x900). This is of course 0x1100 - 0x900 = 0x800
and not 0x200, so the amount of 4-byte integers it can fit is not 0x80
but 0x200. Fix this and make the math more explicit so it can be more
easily factored out and adjusted if that becomes necessary for a future
SoC.

Also fix a dangerous typo in REG_APID_MAP() where the macro would
reference a random variable `i` rather than its argument (`apid`), and
we just got lucky that the only caller in the current code happened to
pass in a variable called `i` as that argument.
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
Change-Id: I049dd044fa5aeb65be0e7b12150afd6eb4bac0fa
      de67080f
    • Avinash Mehta's avatar
      product/tc0: Enable Theodul DSU in TC platform · e5da15e0
      Avinash Mehta authored 
      

Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
Signed-off-by: default avatarAvinash Mehta <avinash.mehta@arm.com>
Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
      e5da15e0
  43. 02 Feb, 2021 1 commit
  45. 29 Jan, 2021 2 commits
    • Pranav Madhu's avatar
      plat/arm/board: enable AMU for RD-N2 · f7bab276
      Pranav Madhu authored 
      

AMU counters are used for monitoring the CPU performance. RD-N2 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).

Change-Id: I5cc749cf63c18fc5c7563dd754c2f42990a97e23
Signed-off-by: default avatarPranav Madhu <pranav.madhu@arm.com>
      f7bab276
    • Pranav Madhu's avatar
      plat/arm/board: enable AMU for RD-V1 · c9bf2cf5
      Pranav Madhu authored 
      

AMU counters are used for monitoring the CPU performance. RD-V1 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).

Change-Id: I4003d21407953f65b3ce99eaa8f496d6052546e0
Signed-off-by: default avatarPranav Madhu <pranav.madhu@arm.com>
      c9bf2cf5