- 15 Jan, 2020 23 commits
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Tejas Patel authored
PM_GET_TRUSTZONE_VERSION API is required to use zynqmp-firmware driver for versal. Add support of PM_GET_TRUSTZONE_VERSION API for versal. Signed-off-by:
Tejas Patel <tejas.patel@xilinx.com> Signed-off-by:
Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ie1c859890096024cc8be67386e3fd0f5f8a4385f
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Wendy Liang authored
Enable IPI mailbox service on versal platform. Signed-off-by:
Wendy Liang <wendy.liang@xilinx.com> Signed-off-by:
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Wendy Liang authored
As IPI mailbox service is common to both ZynqMP and Versal, move it to xilinx/common. Signed-off-by:
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Tejas Patel authored
Add PM IOCTL EEMI. Below PLL related IOCTLs are not available in versal PLM. * IOCTL_SET_PLL_FRAC_MODE * IOCTL_GET_PLL_FRAC_MODE * IOCTL_SET_PLL_FRAC_DATA * IOCTL_SET_PLL_FRAC_DATA PLM has new EEMI APIs for PLL related operations. Call them instead of passing IOCTL API to PLM. For other IOCTL, ATF just pass through IOCTL request to PLM (Platform Loader and Manager). Signed-off-by:
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Tejas Patel authored
Add power down/restart related below API - Force power down - System shutdown Signed-off-by:
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Tejas Patel authored
Add SMC handler for EEMI API calls coming from EL1/EL2. Signed-off-by:
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Tejas Patel authored
Implement below PLL related APIs: - Set PLL parameter - Get PLL parameter - Set PLL mode - Get PLL mode Signed-off-by:
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Tejas Patel authored
Implement below clock related APIs: - Clock enable - Clock disable - Clock get status - Clock set divider - Clock get divider - Clock set parent - Clock get parent Signed-off-by:
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Tejas Patel authored
Implement below pin control related APIs: - Request pin - Release pin - Set pin function - Get pin function - Set pin parameter value - Get pin parameter value Signed-off-by:
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Tejas Patel authored
Implement below reset related APIs: - Reset assert - Get reset status Signed-off-by:
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Tejas Patel authored
Implement below device related PM APIs: - Request device - Release device - Set requirement - Get device status Signed-off-by:
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by:
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Tejas Patel authored
Add support for below suspend related APIs. - self_suspend - abort_suspend - request_suspend Signed-off-by:
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Tejas Patel authored
Add support for EEMI API get_api_verion. Signed-off-by:
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Tejas Patel authored
Port ZynqMP PM services for versal to send PM APIs to PMC using IPI. Signed-off-by:
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Tejas Patel authored
Move versal_def.h to platform specific include directory. Also, update source file to include header file from updated path of versal_def.h Signed-off-by:
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Tejas Patel authored
Move versal_private.h to platform specific include directory. Also, rename it to plat_private.h instead of having platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by:
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Siva Durga Prasad Paladugu authored
- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts to be targeted to EL3. - Raise SGI interrupts for individual CPU cores as GIC API uses CPU num as parameter, not CPU mask. - Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable CPU interface mask work properly for all CPU cores which is required when generating SGI. - Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear GIC interrupt to avoid same interrupt again. Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by:
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Venkatesh Yadav Abbarapu authored
This patch adds support for CRC checksum for IPI data when the macro ZYNQMP_IPI_CRC_CHECK is defined. Signed-off-by:
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by:
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Rajan Vaja authored
Add new QID to get maximum supported divisor by clock. Signed-off-by:
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Ravi Patel authored
Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by:
Ravi Patel <ravi.patel@xilinx.com> Signed-off-by:
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Rajan Vaja authored
Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by:
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Rajan Vaja authored
Add support to add extra custom type flags and provide to caller in topology query. Signed-off-by:
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Rajan Vaja authored
Add GET_CALLBACK_DATA function again as now Linux driver supports both mailbox as well as ISR method. Signed-off-by:
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- 07 Jan, 2020 7 commits
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Rajan Vaja authored
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid clock list would not be registered to CCF framework and so cannot be used as parent of other clocks. WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock). If CLK_TOPSW_LSBUS is not registered, CCF would not recognize that clock and hence rate of WDT clock would be calculated to be 0 by CCF(as parent rate is considered 0). So it is necessary to allow registration of CLK_TOPSW_LSBUS clock. Signed-off-by:
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Mounika Grace Akula authored
This patch adds LPD WDT clock node to the pm_clock clocks structure list so that LPD WDT can be used from Linux. Also this patch removes the CLK_LPD_LSBUS from invalid clock list to allow the registration of this clock to CCF framework as it is the parent of LPD WDT. Signed-off-by:
Mounika Grace Akula <mounika.grace.akula@xilinx.com> Signed-off-by:
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Mirela Simonovic authored
GEM-related clock models were incorrect and are fixed as follows (documented below for GEM0, but the same holds for any GEM ID): - CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this clock is newly introduced in this patch. - CLK_GEM0_REF models the clock mux that selects the reference clock for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL. Note that the routing of external clock to the mux is not modelled and is assumed to be configured by the FSBL if required, and not changeable at runtime. The ID of this clock is introduced in this patch. - CLK_GEM0_TX models clock with only a gate that is controlled via bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID value of CLK_GEM0_REF. This is done in order to fix the clock models and incorrect binding without requiring to change device-tree (binding of clock IDs to GEM interface). - CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced from external RGMII PHY (via MIO or EMIO). We do not model the whole clock path to the Rx gate, since this is configured by the FSBL and never changed at runtime (and there is no mechanism to change the path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX were swapped in device tree, so by fixing the IDs this way there is no need for device tree fix. Rates of the external RX/TX clocks can be specified in device tree if needed. Right now, that's not necessary because Tx clock is sourced from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas the Rx clock is sourced from external reference and the driver never attempts to get/get clock rate (only to enable it). If this changes in future, ATF clock model doesn't need to be changed. Instead, the clock rates for gem0_tx_ext and gem0_rx_ext have to be specified in device tree. Signed-off-by:
Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by:
Will Wong <will.wong@xilinx.com> Signed-off-by:
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Mounika Grace Akula authored
This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT. Signed-off-by:
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Edgar E. Iglesias authored
Correct the syscnt frequency for ZynqMP QEMU to 65Mhz. Signed-off-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by:
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Venkatesh Yadav Abbarapu authored
Add support for zu48dr and zu49dr to the list of zynqmp devices. The zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b and 0x7e. Signed-off-by:
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Siva Durga Prasad Paladugu authored
This patch adds new RFSoC device ZU39DR to zynqmp devices list Signed-off-by:
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- 03 Jan, 2020 2 commits
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Alexei Fedorov authored
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Vishnu Banavath authored
The SCU connects one to four Cortex-A5/Cortex-A9 processors to the memory system through the AXI interfaces. The SCU functions are to: - maintain data cache coherency between the Cortex-A5/Cortex-A9 processors - initiate L2 AXI memory accesses - arbitrate between Cortex-A5/Cortex-A9 processors requesting L2 accesses - manage ACP accesses. Snoop Control Unit will enable to snoop on other CPUs caches. This is very important when it comes to synchronizing data between CPUs. As an example, there is a high chance that data might be cache'd and other CPUs can't see the change. In such cases, if snoop control unit is enabled, data is synchoronized immediately between CPUs and the changes are visible to other CPUs. This driver provides functionality to enable SCU as well as enabling user to know the following - number of CPUs present - is a particular CPU operating in SMP mode or AMP mode - data cache size of a particular CPU - does SCU has ACP port - is L2CPRESENT Change-Id: I0d977970154fa60df57caf449200d471f02312a0 Signed-off-by:Vishnu Banavath <vishnu.banavath@arm.com>
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- 02 Jan, 2020 4 commits
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Alexei Fedorov authored
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Manish Pandey authored
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Alexei Fedorov authored
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Manish Pandey authored
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- 30 Dec, 2019 2 commits
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Manish Pandey authored
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Manish Pandey authored
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- 29 Dec, 2019 2 commits
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Samuel Holland authored
Signed-off-by:Samuel Holland <samuel@sholland.org> Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95
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Samuel Holland authored
Some platforms are extremely memory constrained and must split BL31 between multiple non-contiguous areas in SRAM. Allow the NOBITS sections (.bss, stacks, page tables, and coherent memory) to be placed in a separate region of RAM from the loaded firmware image. Because the NOBITS region may be at a lower address than the rest of BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this region, or el3_entrypoint_common would attempt to invalidate the dcache for the entire address space. New symbols __NOBITS_{START,END}__ are added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the NOBITS region is invalidated separately. Signed-off-by:
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