Commits · 4bd1d3faed7893e8e7d74f82b4b5de7443f434bd · adam.huang / Arm Trusted Firmware

24 Feb, 2017 1 commit

rockchip: rk3399: add support for ddrfreq suspend/resume · 4bd1d3fa

Derek Basehore authored Feb 24, 2017



This patch sets the frequency configuration of the next DRAM DFS index
to the configuration of the current index. This does not perform a
frequency transition. It just configures registers so the training on
resume for both indices will be correct.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

4bd1d3fa

26 Oct, 2016 1 commit

rockchip: add support save/restore configuration for DDR during enter S3 · 2831bc3a

Caesar Wang authored Oct 27, 2016



This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

2831bc3a