- 15 Jun, 2017 1 commit
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Haojian Zhuang authored
Since this mailbox driver is abandoned, remove it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 13 Jun, 2017 1 commit
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Haojian Zhuang authored
Since the type of ADC value is always unsigned int, don't need to check the value with negative value. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 12 Jun, 2017 2 commits
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Masahiro Yamada authored
Add TSP to test BL32 without relying on external projects. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 09 Jun, 2017 1 commit
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Soby Mathew authored
Change-Id: Ia7d731f429e452e4bc9f9a553d7105b6394c621c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 08 Jun, 2017 11 commits
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Soren Brinkmann authored
The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO level print statement. INFO is defined based on LOG_LEVEL. Hence, builds would fail when - DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined - DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used Fixing this by guarding impl with the same condition that guards INFO. Fixes ARM-software/tf-issues#490 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Lin Huang authored
unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need to check wakeup cpu when resume. Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that. Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Derek Basehore authored
This moves the DRAM restore code to PMUSRAM. This is so that the voltage domain that contains the SRAM that it was stored in before may be turned off during system suspend. Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This converts two functions to use for-loops. This saves a bit of space to help moving DRAM resume code to PMUSRAM. Change-Id: Ie6ca490cf50c2ec83335cf1845b337c3e8a47496 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
The removed if statement would make the same check that the for loop it is in does to break out of the for loop, so it doesn't make any sense to keep it there. Change-Id: I819c29f9182e6de1fc47e418aed15ad38e8f9fa9 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This removes the mmio_... function calls to set the multicast bit for the PHY registers when overriding the write leveling values. These are not needed since multicast is set by default when calling the function, and it's also better not to leave the side effect of disabling multicast when exiting the function. Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This removes the phy_dll_bypass_set function as it is unneeded. The values that function sets are saved during suspend, so the proper values will be restored on resume. Change-Id: I17542206c56e639ce8cb6375233145167441d4e2 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This removes the space allocation for the unused PHY register space. For instance in PHY registers 0-127, only 0-90 are used, so don't save the 91-127 registers. This saves about 1.6KB of space. Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Lin Huang authored
The differential signal of DQS need keep low level before gate training. It need enable RPULL and disable PHY side ODT to ensure it when do gate training. But it can not access the PHY registers to do it when perform DFS.So the workaroud as below: It is ensure that the PHY's read gate is landing somewhere in the incoming DQS's pulses before it starts searching for pre-amble window. It need get the rddqs_delay_ps to calculate the start point of gate training for DFS. Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe Signed-off-by: Lin Huang <hl@rock-chips.com>
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- 07 Jun, 2017 4 commits
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Haojian Zhuang authored
Support BL31 on HiKey960 platform. Implement PSCI. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
BL2 loads MCU firmware & BL31 on hikey960 platform. The MCU firmware is used to implement low power feature. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Support BL1 on HiKey960 platform. When recovery mode is detected, BL1 loads NS BL1U that flushs images into UFS. When normal boot mode is detected, BL1 loads BL2. Fix for https://github.com/ARM-software/tf-issues/issues/486 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Vincent Guittot authored
enable PMF service call and instrumetion for hikey platform Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
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- 05 Jun, 2017 2 commits
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Soby Mathew authored
This patch adds the memory map region for the SCMI payload memory and maps the Juno core indices to SCMI power domains via the `plat_css_core_pos_to_scmi_dmn_id_map` array. Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch adds the SCMI driver for communicating with SCP. The power domain management and system power management protocol of the SCMI specification[1] is implemented in the driver. The SCP power management abstraction layer for SCMI for CSS power management is also added. A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI driver over SCPI. [1] ARM System Control and Management Interface v1.0 (SCMI) Document number: ARM DEN 0056A Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 01 Jun, 2017 2 commits
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Jeenu Viswambharan authored
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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David Wang authored
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler. Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 31 May, 2017 4 commits
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Leo Yan authored
This patch is to enable CPU suspend/resume and system level's suspend/resume; also enable system power off state. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Leo Yan authored
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port for cluster 0 in BL31 platform setup flow. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Leo Yan authored
Fix for CPU topology so present the CPU core numbers for two clusters; Base on this fixing, the PSCI can maintain correct power states. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Fix uninitliazed variable in ddr driver code. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 24 May, 2017 8 commits
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Haojian Zhuang authored
Support BL31 and PSCI. Enable multiple cores in PSCI. Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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Haojian Zhuang authored
BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2 is the mcu firmware that is used to scale cpu frequency and switch low power mode. Change-Id: I1621aa65bea989fd125ee8502fd56ef72362bf97 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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Haojian Zhuang authored
Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1. So BL2 will be loaded from eMMC into SRAM later. Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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dp-arm authored
Since ARM_DRAM2_BASE is above the 32-bit limit, the condition is always false. Wrap this condition in an ifndef to avoid warnings during compilation. Change-Id: Ideabb6c65de6c62474ed03eb29df4b049d5316be Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
This function was removed long ago. Remove remaining pragma reference. Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
The default case is impossible to hit as the `power_level` is already checked earlier. Avoids a clang warning. Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3a8ab Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
Change-Id: I4108ce8d1fe7d3fd51a5a96d43b9134c23b8399b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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Antonio Nino Diaz authored
This options enables an implementation of SHA-256 that has a smaller code footprint (~1.6 KB less) but is also ~30% slower. For ARM platforms, code size is currently considered more important than execution speed in the mbed TLS crypto module. Added a small note about this option to the documentation of the authentication framework. Change-Id: I4c0b221ea5d3466465261316ba07b627fa01b233 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 May, 2017 2 commits
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Masahiro Yamada authored
The header tbbr_oid.h contains OIDs obtained by ARM Ltd. so there is no good reason to use platform_oid.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Platforms aligned with TBBR are supposed to use their own OIDs, but defining the same macros with different OIDs does not provide any value (at least technically). For easier use of TBBR, this commit allows platforms to reuse the OIDs obtained by ARM Ltd. This will be useful for non-ARM vendors that do not need their own extension fields in their certificate files. The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the backward compatibility. For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 16 May, 2017 1 commit
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Soby Mathew authored
The commit abd2aba9 introduced a regression to the AArch32 sp_min Juno build. This patch fixes that. Change-Id: I4b141717684d6aee60c761ea17f23170aa6708c3 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 15 May, 2017 1 commit
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Yatharth Kochar authored
Add support for firmware upgrade on AArch32. This patch has been tested on the FVP models. NOTE: Firmware upgrade on Juno AArch32 is not currently supported. Change-Id: I1ca8078214eaf86b46463edd14740120af930aec Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
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