- 29 Mar, 2021 2 commits
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Thomas Abraham authored
The macros defining the SMC function ids for DMC-620 error handling are listed in the sgi_base_platform_def.h header file. But these macros are not applicable for all platforms supported under plat/sgi. So move these macro definitions to sgi_ras.c file in which these are consumed. While at it, remove the AArch32 and error injection function ids as these are unused. Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9
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Thomas Abraham authored
The macros specific to SDEI defined in the sgi_base_platform_def.h are not applicable for all the platforms supported by plat/sgi. So refactor the SDEI specific macros into a new header file and include this file on only on platforms it is applicable on. Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5
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- 26 Mar, 2021 1 commit
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Bharat Gooty authored
Broadcom I2C controller driver. Follwoing API's are supported:- - i2c_init() Intialize ethe I2C controller - i2c_probe() - i2c_set_bus_speed() Set the I2C bus speed - i2c_get_bus_speed() Get the current bus speed - i2c_recv_byte() Receive one byte of data. - i2c_send_byte() Send one byteof data - i2c_read_byte() Read single byte of data - i2c_read() Read multiple bytes of data - i2c_write_byte Write single byte of data - i2c_write() Write multiple bytes of data This driver is verified by reading the DDR SPD data. Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
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- 25 Mar, 2021 1 commit
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Andre Przywara authored
The upcoming refactoring to support the new H616 SoCs will push the A64 build over the edge, by using more than the 48KB of SRAM available. To reduce the code size, set some libfdt options that aim to reduce sanity checks (for saving code space): - ASSUME_LATEST: only allow v17 DTBs (as created by dtc) - ASSUME_NO_ROLLBACK: don't prepare for failed DT additions - ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 24 Mar, 2021 18 commits
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Pankaj Gupta authored
New NXP platform lx2160a-qds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
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Pankaj Gupta authored
New NXP platform lx2160a-rdb(Reference Design Board): - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I9c10dac9d5e67d44a2d94a7a27812220fdcc6ae3
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Pankaj Gupta authored
New NXP platform lx2162aqds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I53bfff85398313082db77c77625cb2d40cd9b1b1
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Pankaj Gupta authored
SoC erratas are handled as part of this commit. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I06f7594d19cc7fc89fe036a8a255300458cb36dd
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Pankaj Gupta authored
- NXP SoC lx2160a needs additional ddr_fip.bin. - There are three types of ddr image that can be created: -- ddr_fip.mk for creating fip_ddr.bin image for normal boot. -- ddr_fip_sb.mk for creating fip_ddr_sec.bin image for NXP CSF based CoT/secure boot. -- ddr_fip_tbbr.mk for creating fip_ddr_sec.bin image for MBEDTLS CoT/secure boot. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I24bff8d489f72da99f64cb79b2114faa9423ce8c
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Pankaj Gupta authored
* NXP SoC is 16 A-72 core SoC. * SoC specific defines are defined in: - soc.def - soc.h * Called for BL2 and BL31 setup, SoC specific setup are implemented in: - soc.c * platform specific helper functions implemented at: - aarch64/lx2160a_helpers.S * platform specific functions used by 'plat/nxp/commpon/psci', etc. are implemented at: - aarch64/lx2160a.S * platform specific implementation for handling PSCI_SYSTEM_RESET2: - aarch64/lx2160a_warm_rst.S Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ib40086f9d9079ed9b22967baff518c6df9f408b8
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Pankaj Gupta authored
- Default header files for: -- plat/nxp/soc-lxxxx/include/soc.h uses: --- soc_default_base_addr.h --- soc_default_base_macros.h -- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses: --- plat_default_def.h: Every macro define can be overidden. -- include/common/tbbr/tbbr_img_def.h uses: --- plat_tbbr_img_def.h: platform specific new FIP image macros. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic50003e27e87891be3cd18bdb4e14a1c7272d492
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Pankaj Gupta authored
For NXP platforms: - Setup files for BL2 and BL31 - Other supporting files. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I36a1183a0652701bdede9e02d41eb976accbb017
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Pankaj Gupta authored
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2 raised from kernel (> 5.4). As part of first cold boot, DDR training data is stored in NV storage. As part of this SMC handling, following things are done: - DDR is put in self-refresh mode to retain the content of DDR. - Reset cause is saved. - Reset is triggered. On next boot to last warm-reset, DDR training is restored from the NV storage. Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I8e4fb0824887af49e959c93825e2ab0ba887fc9d
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Pankaj Gupta authored
NV storage API(s) for NXP platforms, supported on: - flexspi-nor - SecMon - General Purpose Registers at Low-Power section, retains their content if backed by coined battery. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Id65dee4f28e7d6d2024407030039de33ebe0fa05
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Pankaj Gupta authored
NXP SoC supports two TBB mode: - MBED_TLS based -- ROTK key hash is placed as part of the BL2 binary at section: --- .rodata.nxp_rotpk_hash -- Supporting non-volatile counter via SFP. -- platform function used by TFA common authentication code. - NXP CSF based -- ROTK key deployment vary from MBEDTLS Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ib0f0bf024fd93de906c5d4f609383ae9e02b2fbc
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Pankaj Gupta authored
All of the NXP SoC, needs fip_fuse image to be loaded additionally as part of preparation for Trusted board boot - fip_fuse.bin contains an image for auto fuse provisioning. - Auto fuse provisioning is based on the input file with values for: -- SRK Hash -- OTPMK -- misc. refer board manual for more details. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I26d4024fefe352d967ca120191f784f1f47aa9d1
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Pankaj Gupta authored
Few of the NXP SoC like LX2160A, needs ddr-phy images to be loaded additionally before DDR initialization - fip_ddr.bin is created containing upto 6 ddr images. - With TRUSTED_BOARD_BOOT = 1, fip_ddr.bin is authenticated first before loading and starting DDR initialization. - To successfully compile this image, platform-defined header files needs to be defined: -- include/common/tbbr/tbbr_img_def.h uses: --- plat_tbbr_img_def.h: platform specific new FIP image macros. -- include/tools/share/firmware_image_package.h uses: --- plat_def_fip_uuid.h: platform specific new UUID macros. ---- Added UUID for DDR images to create FIP-DDR. ---- Added UUID for FUSE provisioning images to create FIP-fuse. -- include/tools/share/tbbr_oid.h uses: --- platform_oid.h: platform specific new OID macros. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Icbcf1673a8c398aae98680b5016f4276b4864b91
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Pankaj Gupta authored
function load_img(), is dependent on: - Recursively calling load_image() defined in common/bl_common.c - for each image in the fip. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I57ca4b666cd1b0b992b7c0fc2a4260b558c0e2a9
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Pankaj Gupta authored
SMC call handling at EL3 due SIP and SVC calls. Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: If86ee43477fc3b6116623928a3299d4e9015df8c
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Pankaj Gupta authored
Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I9853263ed38fb2a9f04b9dc7d768942e32074719
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Pankaj Gupta authored
Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Idafd8b0d94edf3515e8317431274d77289b7a1d0
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Pankaj Gupta authored
bl31-data file written in assembly helps to manage data at bl31. Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic3ace03364648cc1174bb05b5b334b9ccdaaa4ed
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- 23 Mar, 2021 1 commit
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Samuel Holland authored
This works even on SoCs that do not have an ARISC, and it avoids clobbering whatever ARISC firmware might be running. Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91 Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 22 Mar, 2021 1 commit
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Jan Kiszka authored
Addresses the deprecation warning produced by drivers/arm/gic/common/gic_common.c. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: I1a3ff4835d0f94c74b405db10622e99875ded82b
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- 19 Mar, 2021 1 commit
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Tejas Patel authored
BIT24 of IPI command header is used to determine if caller is secure or non-secure. Mark BIT24 of IPI command header as non-secure if SMC caller is non-secure. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
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- 16 Mar, 2021 1 commit
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Michal Simek authored
Versal is a72 based that's why there is no reason to build low level assemble code for a53. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
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- 15 Mar, 2021 1 commit
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Olivier Deprez authored
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU instantiated in a Secure Partition: -A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs. An EC is pinned to a corresponding physical CPU. -An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to the physical CPU from which the FF-A call is originating. This change permits exercising the latter case within the TF-A-tests framework. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
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- 10 Mar, 2021 1 commit
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Usama Arif authored
Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf
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- 09 Mar, 2021 1 commit
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Heiko Stuebner authored
Compiling BL31 for the Rockchip platform now produces a message about the deprecation of gic_common.c. Follow the advice and use include gicv2.mk instead. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e
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- 08 Mar, 2021 1 commit
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Roger Lu authored
The case for value "VCOREFS_SMC_CMD_INIT" is not terminated by a "break" statement. Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e
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- 03 Mar, 2021 6 commits
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Xi Chen authored
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000; 2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000; Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a
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Roger Lu authored
Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6 Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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Roger Lu authored
Supports dram/mainpll/26m off when system suspend Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32
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Roger Lu authored
Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2
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Roger Lu authored
Low Power Management (LPM) helps find a suitable configuration for letting system entering idle or suspend with the most resources off. Change-Id: Ie6a7063b666cf338cff5bc972c9025b26de482eb Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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Venkatesh Yadav Abbarapu authored
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are 0x7d, 0x78 and 0x7f. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
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- 02 Mar, 2021 1 commit
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Tejas Patel authored
Return timeout error if, IPI is not acked in specified timeout. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
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- 01 Mar, 2021 3 commits
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johpow01 authored
Add basic support for Makalu CPU. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
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Masahisa Kojima authored
This commit fixes the wrong memory type, secure NOR flash shall be mapped as MT_DEVICE. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602
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Masahisa Kojima authored
sbsa-ref in QEMU may create up to 512 cores. This commit prepares the MP information to support 512 cores. The number of xlat tables for spm_mm is also increased. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
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