1. 04 Sep, 2018 3 commits
    • Bryan O'Donoghue's avatar
      warp7: Add initial warp7_helpers.S · 54544c99
      Bryan O'Donoghue authored
      
      
      This commit adds a warp7_helpers.S which contains a implementation of:
      
      - platform_mem_init
      - plat_get_my_entrypoint
      - plat_crash_console_init
      - plat_crash_console_putc
      Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      54544c99
    • Bryan O'Donoghue's avatar
      imx7: hab_arch: Provide a hab_arch.h file · 58254711
      Bryan O'Donoghue authored
      
      
      In order to enable compile time differences in HAB interaction, we should
      split out the definition of the base address of the HAB API.
      
      Some version of the i.MX series have different offsets from the BootROM
      base for the HAB callback table.
      
      This patch defines the header into which we will define the i.MX7 specific
      offset. The offset of the i.MX7 function-callback table is simultaneously
      defined.
      
      Once done, we can latch a set of common function pointer locations from the
      offset given here and if necessary change the offset for different
      processors without any other code-change.
      
      For now all we support is i.MX7 so the only offset being defined is that
      for the i.MX7.
      Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      Reviewed-by: default avatarRyan Harkin <ryan.harkin@linaro.org>
      58254711
    • Bryan O'Donoghue's avatar
      imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms · 7d464592
      Bryan O'Donoghue authored
      
      
      In order to have some common code shared between similar SOCs its pretty
      common to have IP blocks reused. In reusing those blocks we frequently need
      to map compatible blocks to different addresses depending on the SOC.
      
      This patch adds a basic memory map of the i.MX7 based on the "Cortex-A7
      Memory Map" section 2.12 of "i.MX7Solo Applications Processor Reference
      Manual, Rev 0.1 08/2016"
      
      In memory map terms the i.MX7S and i.MX7D are identical with the D
      variant containing two Cortex-A7 cores plus a Cortex-M core and the S
      variant containing one Cortex-A7 and one Cortex-M.
      Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      7d464592