- 24 Jul, 2018 14 commits
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Yann Gautier authored
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs. Signed-off-by:
Yann Gautier <yann.gautier@st.com> Signed-off-by:
Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
Signed-off-by:
Mathieu Belou <mathieu.belou@st.com> Signed-off-by:
Etienne Carriere <etienne.carriere@st.com> Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree. Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by:
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Yann Gautier authored
If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration. Signed-off-by:
Pascal Paillet <p.paillet@st.com>
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Yann Gautier authored
Signed-off-by:
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Yann Gautier authored
This will be used by BL33 to get boot device and instance. Signed-off-by:
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Yann Gautier authored
The management of pinctrl nodes of device tree is also added. Signed-off-by:
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Yann Gautier authored
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/. Signed-off-by:
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Yann Gautier authored
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. STM32MP1 uses BL2 compiled with BL2_AT_EL3. Signed-off-by:
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Yann Gautier authored
Signed-off-by: -
danh-arm authored
synquacer: Enable optional OP-TEE support
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danh-arm authored
Double-fault and fatal error handling support
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Sumit Garg authored
OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by:
Sumit Garg <sumit.garg@linaro.org> Reviewed-by:
Daniel Thompson <daniel.thompson@linaro.org>
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danh-arm authored
hikey: include TBB in BL1
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- 22 Jul, 2018 1 commit
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Haojian Zhuang authored
BL1 is used in recovery mode on HiKey. The TBB implementation on HiKey is in BL2. It means that user need to build ATF BL2 with TBB and ATF BL1 with non-TBB. It's inconvenient. So include TBB in BL1, too. Signed-off-by:
Teddy Reed <teddy@prosauce.org> Signed-off-by:
Victor Chong <victor.chong@linaro.org> Signed-off-by:
Haojian Zhuang <haojian.zhuang@linaro.org>
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- 19 Jul, 2018 9 commits
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danh-arm authored
Marvell support for Armada 8K SoC family
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danh-arm authored
rpi3: PSCI and Linux boot improvements
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danh-arm authored
xlat: More refactoring
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danh-arm authored
hikey: Add experimental TBB support
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danh-arm authored
Misc arch.h fixes and cleanup
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Jeenu Viswambharan authored
Change-Id: I76cb1d387ab51ee48fa91fd7458c7041b454ceee Signed-off-by:Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
External Aborts while executing in EL3 is fatal in nature. This patch allows for the platform to define a handler for External Aborts received while executing in EL3. A default implementation is added which falls back to platform unhandled exception. Change-Id: I466f2c8113a33870f2c7d2d8f2bf20437d9fd354 Signed-off-by: -
Jeenu Viswambharan authored
Double fault is when the PE receives another error whilst one is being handled. To detect double fault condition, a per-CPU flag is introduced to track the status of error handling. The flag is checked/modified while temporarily masking external aborts on the PE. This patch routes double faults to a separate platform-defined handler. Change-Id: I70e9b7ba4c817273c55a0af978d9755ff32cc702 Signed-off-by: -
Jeenu Viswambharan authored
Uncontainable errors are the most severe form of errors, which typically mean that the system state can't be trusted any more. This further means that normal error recovery process can't be followed, and an orderly shutdown of the system is often desirable. This patch allows for the platform to define a handler for Uncontainable errors received. Due to the nature of Uncontainable error, the handler is expected to initiate an orderly shutdown of the system, and therefore is not expected to return. A default implementation is added which falls back to platform unhandled exception. Also fix ras_arch.h header guards. Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55 Signed-off-by:
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- 18 Jul, 2018 16 commits
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Konstantin Porotchkin authored
Add support for BLx stages to use libraries in MAKE_BL macro. This change does not affect BL stages that do not have BL_LIBS variable defined in their makefiles. However in case that BL wants to use external library (for instance vendor-specific DDR initialization code supplied as a library), this patch will allow to build BL image linked with such library. Change-Id: Ife29069a72dc4aff833db6ef8b828736d6689b78 Signed-off-by:Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Remove assert on buffer address equal zero. Marvell uses address 0x0 for loading BL33, so this check is irrelevant and breaks the debug builds on Marvell platforms. Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125 Signed-off-by:
Haim Boot <hayim@marvell.com> Signed-off-by:
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Konstantin Porotchkin authored
Add support for A8K platform boards Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8 Signed-off-by:
Hanna Hawa <hannah@marvell.com> Signed-off-by:
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Konstantin Porotchkin authored
Add common Marvell ARMADA platform components. This patch also includes common components for Marvell ARMADA 8K platforms. Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf Signed-off-by:
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Konstantin Porotchkin authored
Change-Id: I341440701b7e5e3555e604dd9d0a356795e6c4fb Signed-off-by:
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Konstantin Porotchkin authored
Add Marvell "doimage" utility support. The "doimage" utility allows to create flash images compatible with Marvell BootROM image format. Additionally this tool allows the flash image parsing and verification. Change-Id: Ie8d7ccd0cc2978684e7eecb695f375395fc749ee Signed-off-by: -
Konstantin Porotchkin authored
Add i2c driver for A8K SoC family. Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196 Signed-off-by:
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Konstantin Porotchkin authored
Add COMPHY driver for usage in a runtime service. Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by:
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Konstantin Porotchkin authored
Add thermal driver for A8K SoC family. The termal unit data is used by Marvell DRAM initialization code for optimizing the memory controller configuration Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73 Signed-off-by:
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Konstantin Porotchkin authored
Add LLC (L3) cache management drivers for Marvell SoCs AP806, AP807 and AP810 Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894 Signed-off-by:
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Konstantin Porotchkin authored
Add definition of EL1 L2 Auxilary Control register to Cortex A72 library headers. Signed-off-by: -
Konstantin Porotchkin authored
Add ModularChip and MCI drivers for A8K SoC family. ModularChip drivers include support for the internal building blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110 Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02 Signed-off-by:
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Konstantin Porotchkin authored
Add address decoding unit drivers for Marvell SoCs. Address decoding flow and address translation units chart are located at docs/marvell/misc/mvebu-a8k-addr-map.txt Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed Signed-off-by:
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Konstantin Porotchkin authored
Signed-off-by: -
Soby Mathew authored
Add i.MX8QX/i.MX8QM power management feature
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Sandrine Bailleux authored
Change-Id: I98f23f6cebcf984b57efc5449b75ff702e1984a0 Signed-off-by:Sandrine Bailleux <sandrine.bailleux@arm.com>
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