- 19 Jun, 2020 10 commits
-
-
Konstantin Porotchkin authored
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Extend the CCU tables with secure SRAM window in all board setups that uses SoCs based on AP806/AP807 North Bridges Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Marcin Wojtas authored
It is not needed to reserve 64MB for FIP. Limit this to 4MB for both supported Armada SoC families. Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Extract from bigger commit] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-
Konstantin Porotchkin authored
- Remove TRUSTED_DRAM_BASE TRUSTED_DRAM_SIZE MARVELL_TRUSTED_SRAM_BASE - Rename PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_* PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_* MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM - Move MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h - Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map - Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM - Add minor style improvents Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Improve patch after rebase] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-
Konstantin Porotchkin authored
Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Make all LLC-related macros to start with the same prefix Add more LLC control registers definitions This patch is a preparation step for LLC SRAM support Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Ben Peled authored
The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com>
-
Konstantin Porotchkin authored
As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-
Grzegorz Jaszczyk authored
The phy porting layer uses defaults defined in "phy-default-porting-layer.h" when board specific file "phy-porting-layer.h" is not found. Because of the regression the board specific directory was not included, therefore all boards used default parameters. Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
Before this patch the configuration took place only for CP0 and CP1, but since new platforms can contains up to 3 CPs update is required. Change-Id: Iebd50bbe7b9772063e2c4efb3a7ecbfd593e950d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
- 18 Jun, 2020 1 commit
-
-
Marcin Wojtas authored
The Marvell Armada 37xx SoCs-based platforms contain a bit awkward directory structure because the currently only one supported PLAT and PLAT_FAMILY are the same. Modify the latter to 'a3k' in order to improve it and keep plat/marvell/armada tree more consistent: plat/marvell/ ├── armada │ ├── a3k │ │ ├── a3700 [...] │ ├── a8k │ │ ├── a70x0 [...] Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-
- 06 Jun, 2020 11 commits
-
-
Alex Leibovich authored
Change a topology map from internal database to SPD based for 32bit bus width mode Change-Id: I803166893ddc2fd916fc8a1c27fffd34b6ec0c72 Signed-off-by: Alex Leibovich <alexl@marvell.com>
-
Alex Leibovich authored
Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com>
-
Alex Leibovich authored
This commit introduces 32-bit DDR topology map initialization. For that purpose a new DDR32 build flag is added, with according documentation update. Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01 Signed-off-by: Alex Leibovich <alexl@marvell.com>
-
Grzegorz Jaszczyk authored
This commit introduces two changes: - remove hardcoded references to mci0 from the driver - perform mci optimization for all mci interfaces It fixes performance issues observed on cn9132 CP2. Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
The mci_initialize function name was misleading. The function itself doesn't initialize MCI in general but performs MCI link tuning for performance improvement. Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
Change-Id: Id702c070c433f8439faad115830e71b2873ab70a Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
Snoop filter needs to be enabled once per cluster. Change-Id: I241e72f21982142ba290c7547df6f434e6a6a98d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
By default all external CPs start with configuration address space set to 0xf200_0000. To overcome this issue, go in the loop and initialize the CP one by one, using temporary window configuration which allows to access each CP and update its configuration space according to decoding windows scheme defined for each platform. In case of cn9130 after this procedure bellow addresses will be used: CP0 - f2000000 CP1 - f4000000 CP2 - f6000000 When the re-configuration is done there is need to restore previous decoding window configuration(init_io_win). Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
As a preparation for upcoming support for CN9130 platform, which is classified as OcteonTx2 product but inherits functionality from a8k, allow to use a8k_common.mk and mss_common.mk from outside of PLAT_FAMILY_BASE. Above is done by introducing BOARD_DIR which needs to be set by each platform, before including a8k_common.mk and mss_common.mk. This will allow to use mentioned mk files not only for platforms located under previously defined PLAT_FAMILY_BASE. Change-Id: I22356c99bc0419a40ae11e42f37acd50943ea134 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-
- 03 Jun, 2020 1 commit
-
-
Marcin Wojtas authored
BL31_CACHE_DISABLE flag was introduced as a work-around for the older SoC revisions. Since it is not relevant in the newest versions, toggle it to be disabled by default. One can still specify it by adding 'BL31_CACHE_DISABLE=1' string to the build command. Change-Id: I11b52dade3ff7f8ee643b8078c6e447c45946570 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
-
- 30 Mar, 2020 1 commit
-
-
Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
- 10 Mar, 2020 1 commit
-
-
Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
- 25 Feb, 2020 3 commits
-
-
Andre Przywara authored
Now that different UARTs share the same console_t struct, we can simplify the console selection for the Marvell platforms: We share the same console_t pointers, just change the name of the console register functions, depending on the selected platform. Change-Id: I6fe3e49fd7f208a9b3372c5deef43236a12867bc Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
- 30 Jan, 2020 2 commits
-
-
Grzegorz Jaszczyk authored
Extend possible images to 8, additionaly add another type which will be used with platform containing up to 3 CPs. Change-Id: Ib68092d11af9801e344d02de839f53127e056e46 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
In order to access MG SRAM, the amb bridge needs to be configured which is done in bl2 platform init. For MG CM3, the image is only loaded to its SRAM and the CM3 itself is left in reset. It is because the next stage bootloader (e.g. u-boot) will trigger action which will take it out of reset when needed. This can happen e.g. when appropriate device-tree setup (which has enabled 802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be running. Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
- 24 Jan, 2020 1 commit
-
-
Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7d660d5a9d7e44601353c77e9b6ee4096a277d76
-
- 15 Jan, 2020 1 commit
-
-
Luka Kovacic authored
Implements a way to add platform specific power off code to a Marvell Armada 8K platform. Marvell Armada 8K boards can now add a board/system_power.c file that contains a system_power_off() function. This function can now send a command to a power management MCU or other board periferals before shutting the board down. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db --- I am working on a device that will be ported later, which has a custom power management MCU that handles LEDs, board power and fans and requires this separation.
-
- 03 Oct, 2019 1 commit
-
-
Lionel Debieve authored
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
-
- 01 Aug, 2019 1 commit
-
-
Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 16 Jul, 2019 2 commits
-
-
Remi Pommarel authored
When the link goes down (e.g. during a retrain), accessing the device configuration space can trigger an ARM64 SError interrupt. Such conditions cannot be predicted, so to avoid a crash the SError is ignored. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Change-Id: I2b1fd3296cc1c88b9ca1fe21c0924cb324eed58d
-
Remi Pommarel authored
Use v2 xlat tables library instead of v1 for marvell platforms. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Change-Id: I838a6a878a8353e84eea9529721761b478943f0a
-
- 11 Jul, 2019 1 commit
-
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
- 28 Jun, 2019 1 commit
-
-
Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
-
- 05 Apr, 2019 2 commits
-
-
Grzegorz Jaszczyk authored
There is no need to rely on x1 argument. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Change-Id: Ie7766e801e724801b42b66331ba252ede5744a2c
-
Grzegorz Jaszczyk authored
The argument passed via x1 is used as a base address for comphy related routines. Nevertheless validation of this address wasn't good enough and allowed some non comphy related addresses to slip over. To overcome this issue make sure that the address passed via SMC points to valid CP range and allow to proceed comphy initializations only with correct comphy offset. This could be fixed in a different way e.g. by passing CP id from the caller, but since this API is already used with various Linux, U-Boot and UEFI versions it can't be changed. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Change-Id: Ia74dbc36efcfbefc4a102d31191e6af5808c4a82
-