1. 02 Jun, 2021 1 commit
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART parent clock rate determination · 5a91c439
      Pali Rohár authored
      
      
      The UART code for the A3K platform assumes that UART parent clock rate
      is always 25 MHz. This is incorrect, because the xtal clock can also run
      at 40 MHz (this is board specific).
      
      The frequency of the xtal clock is determined by a value on a strapping
      pin during SOC reset. The code to determine this frequency is already in
      A3K's comphy driver.
      
      Move the get_ref_clk() function from the comphy driver to a separate
      file and use it for UART parent clock rate determination.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
      5a91c439
  2. 19 Jun, 2020 2 commits
  3. 18 Jun, 2020 1 commit
    • Marcin Wojtas's avatar
      plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs · b5c850d4
      Marcin Wojtas authored
      
      
      The Marvell Armada 37xx SoCs-based platforms contain a bit
      awkward directory structure because the currently only one
      supported PLAT and PLAT_FAMILY are the same. Modify the latter
      to 'a3k' in order to improve it and keep plat/marvell/armada
      tree more consistent:
      
      plat/marvell/
      ├── armada
      │   ├── a3k
      │   │   ├── a3700
      
      [...]
      
      │   ├── a8k
      │   │   ├── a70x0
      
      [...]
      
      Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a
      Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
      b5c850d4