1. 26 Jan, 2015 1 commit
    • Yatharth Kochar's avatar
      Call reset handlers upon BL3-1 entry. · 79a97b2e
      Yatharth Kochar authored
      This patch adds support to call the reset_handler() function in BL3-1 in the
      cold and warm boot paths when another Boot ROM reset_handler() has already run.
      
      This means the BL1 and BL3-1 versions of the CPU and platform specific reset
      handlers may execute different code to each other. This enables a developer to
      perform additional actions or undo actions already performed during the first
      call of the reset handlers e.g. apply additional errata workarounds.
      
      Typically, the reset handler will be first called from the BL1 Boot ROM. Any
      additional functionality can be added to the reset handler when it is called
      from BL3-1 resident in RW memory. The constant FIRST_RESET_HANDLER_CALL is used
      to identify whether this is the first version of the reset handler code to be
      executed or an overridden version of the code.
      
      The Cortex-A57 errata workarounds are applied only if they have not already been
      applied.
      
      Fixes ARM-software/tf-issue#275
      
      Change-Id: Id295f106e4fda23d6736debdade2ac7f2a9a9053
      79a97b2e
  2. 04 Nov, 2014 1 commit
    • Soby Mathew's avatar
      Use the BL3-1 runtime console as the crash console. · ce6ee933
      Soby Mathew authored
      This patch reassigns the crash console on Juno and FVP to use the runtime
      BL3-1 console. The crash console is changed to SoC UART0 (UART2) from the
      previous FPGA UART0 (UART0) on Juno. In FVP, it is changed from UART0 to
      UART1.
      
      Fixes ARM-software/tf-issues#256
      
      Change-Id: I7df54f86ca00ec2652c27261dd66a94c12610816
      ce6ee933
  3. 21 Aug, 2014 2 commits
    • Juan Castillo's avatar
      Juno: Read primary CPU MPID from SCC GPR_1 · 38af430a
      Juan Castillo authored
      This patch removes the PRIMARY_CPU definition hardcoded in the
      Juno port. Instead, the primary CPU is obtained at runtime by
      reading the SCC General Purpose Register 1 (GPR_1), whose value
      is copied by the SCP into shared memory during the boot process.
      
      Change-Id: I3981daa92eb7142250712274cf7f655b219837f5
      38af430a
    • Sandrine Bailleux's avatar
      Juno: Implement initial platform port · 01b916bf
      Sandrine Bailleux authored
      This patch adds the initial port of the ARM Trusted Firmware on the Juno
      development platform. This port does not support a BL3-2 image or any PSCI APIs
      apart from PSCI_VERSION and PSCI_CPU_ON. It enables workarounds for selected
      Cortex-A57 (#806969 & #813420) errata and implements the workaround for a Juno
      platform errata (Defect id 831273).
      
      Change-Id: Ib3d92df3af53820cfbb2977582ed0d7abf6ef893
      01b916bf