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  1. 08 Nov, 2018 3 commits
  3. 01 Nov, 2018 4 commits
  5. 31 Oct, 2018 2 commits
  7. 30 Oct, 2018 5 commits
  9. 29 Oct, 2018 5 commits
    • Antonio Nino Diaz's avatar
      plat/arm: Fix MISRA defects in SiP SVC handler · 15b94cc1
      Antonio Nino Diaz authored 
      

No functional changes.

Change-Id: I9b9f8d3dfde08d57706ad5450de6ff858a55ac01
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      15b94cc1
    • Deepak Pandey's avatar
      plat/arm: Introduce the N1SDP. · 80d37c28
      Deepak Pandey authored 
      

This patch adds support for the N1SDP (NeoVerse N1 System Development
Platform). It is an initial port and additional features are expected
to be added later.

The port includes only BL31 support as the System Control Processor
(SCP) is expected to take the role of primary boatloader

Change-Id: Ife17d8215a7bfcc1420204a72205e7ef920d0c10
Signed-off-by: default avatarDeepak Pandey <Deepak.Pandey@arm.com>
      80d37c28
    • Soby Mathew's avatar
      FVP: Enable PIE for RESET_TO_BL31=1 · fc922ca8
      Soby Mathew authored 
      

This patch enabled PIE for FVP when RESET_TO_BL31=1. The references
to BL31_BASE are replaced by BL31_START as being a symbol exported by
the linker, will create a dynamic relocation entry in .rela.dyn and
hence will be fixed up by dynamic linker at runtime. Also, we disable
RECLAIM_INIT_CODE when PIE is enabled as the init section overlay
creates some static relocations which cannot be handled by the
dynamic linker currently.

Change-Id: I86df1b0a8b2a8bbbe7c3f3c0b9a08c86c2963ec0
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      fc922ca8
    • Soby Mathew's avatar
      plat/arm: Use `mov_imm` macro to load immediate values · bd83b396
      Soby Mathew authored 
      

This patch makes use of mov_imm macro where possible to load
immediate values within ARM platform layer.

Change-Id: I02bc7fbc1fa334c9fccf76fbddf515952f9a1298
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      bd83b396
    • Soby Mathew's avatar
      Add helper to return reference to a symbol · 6a7b3005
      Soby Mathew authored 
      

This patch adds a utility function to return
the address of a symbol. By default, the compiler
generates adr/adrp instruction pair to return
the reference and this utility is used to override
this compiler generated to code and use `ldr`
instruction.

This is needed for Position Independent Executable
when it needs to reference a symbol which is constant
and does not depend on the execute address of the
binary.

For example, on the FVP, the GICv3 register context is
stored in a secure carveout (arm_el3_tzc_dram) within
DDR and does not relocate with the BL image. Now if
BL31 is executing at a different address other than
the compiled address, using adrp/adr instructions to
reference this memory will not work as they generate an
address that is PC relative. The way to get around this
problem is to reference it as non-PC relative (i.e
non-relocatable location) via `ldr` instruction.

Change-Id: I5008a951b007144258121690afb68dc8e12ee6f7
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      6a7b3005
  11. 26 Oct, 2018 8 commits
  13. 25 Oct, 2018 6 commits
    • Antonio Nino Diaz's avatar
      Deprecate weak crash console functions · e74afb65
      Antonio Nino Diaz authored 
      

The default behaviour of the plat_crash_console_xxx functions isn't
obvious to someone that hasn't read all the documentation. As they are
not mandatory, it is unlikely that the code will be checked when doing a
platform port, which may mean that some platforms may not have crash
console support at all.

The idea of this patch is to force platform maintainers to decide how
the crash console has to behave so that the final behaviour isn't
unexpected.

Change-Id: I40b2a7b56c5530c1dcd63eace5bd37ae6335056e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      e74afb65
    • Antonio Nino Diaz's avatar
      rockchip: Use common crash console functions · a9d5a3ff
      Antonio Nino Diaz authored 
      

This platform depends on weak functions defined in
``plat/common/aarch64/platform_helpers.S`` that are going to be removed.

Change-Id: I5104d091c32271d77ed9690e9dc257c061289def
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      a9d5a3ff
    • Antonio Nino Diaz's avatar
      Add sample crash console functions · 6c9ada31
      Antonio Nino Diaz authored 
      

Platforms that wish to use the sample functions have to add the file to
their Makefile. It is not included by default.

Change-Id: I713617bb58dc218967199248f68da86241d7ec40
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      6c9ada31
    • Antonio Nino Diaz's avatar
      plat/arm: Make crash console functions strong · c02c69f8
      Antonio Nino Diaz authored 
      

In Arm platforms the crash console doesn't print anything if the crash
happens early enough. This happens in all images, not only BL1. The
reason is that they the files ``plat/common/aarch64/platform_helpers.S``
and ``plat/arm/common/aarch64/arm_helpers.S``, and the crash console
functions are defined as weak in both files. In practice, the linker
can pick the one in ``plat/common``, which simply switches the multi
console to crash mode when it wants to initialize the crash console.
In the case of Arm platforms, there are no console drivers registered
at that point, so nothing is printed.

This patch makes the functions in plat/arm strong so that they override
the weak functions in plat/common.

Change-Id: Id358db7d2567d7df0951790a695636cf6c9ac57f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c02c69f8
    • Antonio Nino Diaz's avatar
      Add plat_crash_console_flush to platforms without it · 9c675b37
      Antonio Nino Diaz authored 
      

Even though at this point plat_crash_console_flush is optional, it will
stop being optional in a following patch.

The console driver of warp7 doesn't support flush, so the implementation
is a placeholder.

TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but
they weren't global so they weren't actually used. Also, they were
calling the wrong functions.

imx8_helpers.S only has placeholders for all of the functions.

Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      9c675b37
    • Antonio Nino Diaz's avatar
      zynqmp: Remove dependency on arm_helpers.S · bde25ae2
      Antonio Nino Diaz authored 
      

Non-Arm platforms shouldn't use Arm platform code. This patch copies the
implementation of the functions in arm_helpers.S to zynqmp_helpers.S to
remove this dependency of zynqmp on Arm platforms.

Change-Id: Ia85f303c4c63bcf0ffa57c7f3ef9d88376729b6b
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      bde25ae2
  15. 24 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      rpi3: Add mem reserve region to DTB if present · 5341b42e
      Antonio Nino Diaz authored 
      

When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the memory reserved for the Trusted Firmware, pass it on the DTB.

The current code deletes the memory reserved for the default bootstrap
of the Raspberry Pi and adds the region used by the Trusted Firmware.

This system replaces the previous one consisting on adding
``memmap=16M$256M`` to the Linux command line. It's also meant to be
used by U-Boot and any other bootloader that understands DTB files.

Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      5341b42e
  17. 23 Oct, 2018 2 commits
    • Antonio Nino Diaz's avatar
      juno: Increase BL2 max size · 472158f6
      Antonio Nino Diaz authored 
      

Version 1.4.7 of libfdt is bigger than the current one (1.4.2) and the
current reserved space for BL2 in Juno isn't enough to fit the Trusted
Firmware when compiling with clang or armclang.

Change-Id: I7b73394ca60d17f417773f56dd5b3d54495a45a8
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      472158f6
    • Antonio Nino Diaz's avatar
      tzc: Fix MISRA defects · af6491f8
      Antonio Nino Diaz authored 
      

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.

Also, fix some address definitions in arm_def.h.

Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      af6491f8
  19. 22 Oct, 2018 1 commit
  21. 20 Oct, 2018 3 commits
    • Andre Przywara's avatar
      allwinner: Use the arisc to turn off ARM cores · 7db0c960
      Andre Przywara authored 
      

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      7db0c960
    • Andre Przywara's avatar
      allwinner: Prepare for executing code on the management processor · 11480b90
      Andre Przywara authored 
      

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM cores,
but runs on a separate power domain. This is meant to handle power
management with the ARM cores off.
There are efforts to run sophisticated firmware on that core
(communicating via SCPI with the ARM world), but for now can use it for
the rather simple task of helping to turn the ARM cores off. As this
cannot be done by ARM code itself (because execution stops at the
first of the three required steps), we can offload some instructions to
this management processor.
This introduces a helper function to hand over a bunch of instructions
and triggers execution. We introduce a bakery lock to avoid two cores
trying to use that (single) arisc core. The arisc code is expected to
put itself into reset after is has finished execution.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      11480b90
    • Andre Przywara's avatar
      allwinner: PMIC: AXP803: Delay activation of DC1SW switch · ccd3ab2d
      Andre Przywara authored 
      

There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To avoid this situation, delay the activation of the DC1SW line until
the very end, so those other lines are always activated earlier.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      ccd3ab2d