1. 23 Mar, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra186: check MCE firmware version during boot · 5cb89c56
      Varun Wadekar authored
      
      
      This patch checks that the system is running with the supported MCE
      firmware during boot. In case the firmware version does not match the
      interface header version, then the system halts.
      
      Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5cb89c56
    • Varun Wadekar's avatar
      Tegra186: mce: enable LATIC for chip verification · 66ec1125
      Varun Wadekar authored
      
      
      This patch adds a new interface to allow for making an ARI call that
      will enable LATIC for the chip verification software harness.
      
      LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
      used for various measurements relevant ot particular locations in
      Silicon. They are small counters which can be polled to determine
      how fast a particular location in the Silicon is.
      
      Original change by Guy Sotomayor <gsotomayor@nvidia.com>
      
      Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      66ec1125
  2. 22 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored
      
      
      This patch adds the chip level support for System Suspend entry
      and exit. As part of the entry sequence we first query the MCE
      firmware to check if it is safe to enter system suspend. Once
      we get a green light, we save hardware block settings and enter
      the power state. As expected, all the hardware settings are
      restored once we exit the power state.
      
      Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
  3. 20 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: mce: driver for the CPU complex power manager block · 7808b06b
      Varun Wadekar authored
      
      
      The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
      offload engine for BPMP to do voltage related sequencing and for
      hardware requests to be handled in a better latency than BPMP-firmware.
      
      There are two interfaces to the MCEs - Abstract Request Interface (ARI)
      and the traditional NVGINDEX/NVGDATA interface.
      
      MCE supports various commands which can be used by CPUs - ARM as well
      as Denver, for power management and reset functionality. Since the
      linux kernel is the master for all these scenarios, each MCE command
      can be issued by a corresponding SMC. These SMCs have been moved to
      SiP SMC space as they are specific to the Tegra186 SoC.
      
      Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7808b06b