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This ARI call enables the EDBGREQ feature in the CCPLEX,
which will cause the CPUs to enter debug state instead of
vectoring to sw (ie MCA handler) upon receiving an async
abort signal.

Change-Id: Ifcb0e11446b6ac55179e3350d8f02b60ba32c94d
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates the ARI header file to v3.1.

Change-Id: I3e58cf50d27fb6e72062bb9d9782b75296b32025
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: Ib67eda64b09f26fb2f427f0d624f057081473132
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but future platforms might not support it.

Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a new config to enable MC settings for the AFIW
and AFIR devices. Platforms must enable this config on their own.

Change-Id: I53b450117e4764ea76d9347ee2928f9be178b107
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the smmu driver introduced by the Tegra186 port
to tegra/common so that future chips can (re)use it.

Change-Id: Ia44c7f2a62fb2d8869db3a44742a8c6b13c49036
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch splits the MCE driver into public and private interfaces
to allow usage of common functionality across multiple SoCs.

Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

rockchip/rk3399: the printf changed to tf_printf for console output

Tegra186 platform support v4

The printf() isn't used by the firmware itself, just by the tools under
the ./tools/ folder. Then tf_printf will unconditionally print.
Remove the unused print_dram_status_info() function.

Change-Id: Ie699ccb54a5be9a2cbbd7b8d4193b57075a2f57a
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Fix ARM_BL31_IN_DRAM build

rockchip: Remove unused rockchip_pd_pwr_down_wfi function

Add support for GCC stack protection

Enable all A53 and A57 errata workarounds for Juno

This patch moves the TSA block's macros from memctrl_v2.h to
tegra_def.h in the Tegra186 tree.

Change-Id: I8b45dd3905c5d1f33ffb36d8b2de72aeb06674aa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the chip specific memory controller driver defines to
the appropriate tegra_def.h files, for future compatibility.

Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.

Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Remove stream ID overrides for AON. AON drives its own stream ID when
accesing IOVA memory. However, it needs to use a physical stream ID when
accesing GSC memory. Overriding stream ids prevents AON from accessing
GSC memory, so remove them to allow AON to access GSCs.

Change-Id: Ia2b11014d9780c4546b5e781621ae4cd413735cc
Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch reverts the APE overrides added for chip verification.

Change-Id: Ib85560934d63f6e41e95ef6898a341f24761a517
Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates wake time of the cpu to use the MSBs and zero
out the LSB's. Only 24 out of 32 bits are currently passed
through the PSCI interface. Previously all the LSB's were used.

Change-Id: Ie2d9d1bf6e3003dd47526a124f64e6ad555d2371
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with
request_lo/hi set to zero. MTS automatically takes the reset
vector from MISCREG_AA64_RST register and does not need it to
be passed as parameters.  This patch updates the API and the
caller function accordingly.

Change-Id: Ie3e3402d93951102239d988ca9f0cdf94f290d2f
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

When entering C7, ATF disables caches and flushes the L1 cache. However,
wake_time[cpu] can still remain in the L2 cache, causing later reads to it
to fetch from DRAM. This will read stale values.

Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it
before disabling caches.

Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311
Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates the ARI header to version 3.0

Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Upgrade mbed TLS version

Include all makefiles before build option checks

The TZRAM memory loses its state during "System Suspend". This patch
check if TZRAM base address contains valid data, to decide if the system
is exiting from "System Suspend". To enable TZDRAM encryption, the Memory
Controller's TZDRAM base/size registers would be populated by the BPMP
when the system "wakes up".

Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This change adds function to invoke for MISC_CCPLEX ARI calls and
the corresponding smc handler. This can be used to enable/disable
Coresight clock gating.

Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Save TZDRAM settings for SC7 resume firmware to restore.

SECURITY_BOM:     MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0
SECURITY_BOM_HI:  MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1
SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1

Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the incorrect return value that was being passed
back for the ENUM_FEATURES ARI call.

Change-Id: I3842c6ce27ea24698608830cf4c12cfa7ff64421
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch clears the unused or reserved ARI input registers
before issuing the actual ARI command.

Change-Id: I454b86566bfe088049a5c63527c1323d7b25248a
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Re-factor header files for easier PSCI library integration

Tegra186 platform support v3

The rockchip_pd_pwr_down_wfi function is currently unused, which may
trigger compiler warnings or errors. Remove it.

Change-Id: I7e1b0ae092e8855528ac2065ecefc8bd45305f31
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

Some header files using the ULL() macro were not directly including
utils.h where the macro definition resides. As a consequence, a linker
script with values using this macro did not see the macro definition
and kept the "ULL(<value>)" call in the preprocessed file, which lead to
link error.

Files using ULL() macro now include utils.h directly.

Change-Id: I433a7f36bd21a156c20e69bc2a2bb406140ebdf9
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

mbedtls: Namespace TF specific macros

Change-Id: I7f3e4bfd46613c6311ba4015d56705414fd6feab
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

This function fills the buffer (first argument) with the specified
number of bytes (second argument) from the trusted entropy source.

This function will be used to initialize the stack protector canary.

Change-Id: Iff15aaf4778c13fa883ecb5528fcf9b8479d4489
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Change-Id: If88270bc9edb32634a793b1e1be6c4829f39b9c5
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Introduce new build option ENABLE_STACK_PROTECTOR. It enables
compilation of all BL images with one of the GCC -fstack-protector-*
options.

A new platform function plat_get_stack_protector_canary() is introduced.
It returns a value that is used to initialize the canary for stack
corruption detection. Returning a random value will prevent an attacker
from predicting the value and greatly increase the effectiveness of the
protection.

A message is printed at the ERROR level when a stack corruption is
detected.

To be effective, the global data must be stored at an address
lower than the base of the stacks. Failure to do so would allow an
attacker to overwrite the canary as part of an attack which would void
the protection.

FVP implementation of plat_get_stack_protector_canary is weak as
there is no real source of entropy on the FVP. It therefore relies on a
timer's value, which could be predictable.

Change-Id: Icaaee96392733b721fa7c86a81d03660d3c1bc06
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>