GitLab

ZynqMP Updates

spd: dispatcher for interacting with the Trusty TEE

Cosmetic change to exception table

Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide

The API description currently states that interrupt handlers
(interrupt_type_handler_t pointers) SHOULD return a pointer
to the target cpu_context.

This patch rewords the description of the interrupts handlers to state
that it MUST return a pointer to the target security context. It also
warns about potential portability issue. Specifically, this pointer is
not used on AArch64 and calls to context library APIs must be used to
ask BL31 to return to a specific context. However, this could change in
the future and interrupt handlers must always return the pointer.

Change-Id: I3f82a046de4d7a5b51a8cbebe7eb2a00dbbdb4f0
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

The callback IRQ is delivered to the NS OS. Provide an interface to
allow the NS OS to obtain the callback data from the secure HW.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

The IPI hardware is secure and managed by ATF, nevertheless we deliver
the IRQ to the rich OS. The IRQ is needed to receive PM callbacks.
Enable the IPI interrupt when the rich OS probes the API version.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Remove dead code pieces and stale comments.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Cc: Michal Simek <michal.simek@xilinx.com>
Reported-by: Jonas Karlsson <jonas.karlsson@atero.se>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Use the PMUFW get_chipid call to obtain IDCODE and version register.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Allow reading more than just a single value from the message buffer.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

On ZynqMP the FSBL will configure the system counter. Hence, remove the
initialization of the system counter with hardcoded values from the ATF
and use the setup provided by the bootloader.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

Document plat_psci_ops.(system_off|system_reset)

firmware-design.md: Fix broken link

Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR

* Move comments on unhandled exceptions at the right place.
* Reformat the existing comments to highlight the start of
  each block of 4 entries in the exception table to ease
  navigation (lines of dash reserved for head comments).
* Reflow comments to 80 columns.

Change-Id: I5ab88a93d0628af8e151852cb5b597eb34437677
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

Fix a link broken by a missing space that turned
it into a link to an non-existent anchor.

Change-Id: Ie863e963db28afa3a28b69d3f63bd7638bdf5af9
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

fixes ARM-Software/tf-issues#346

Change-Id: I946c8eab650bba7407775462ce91f394d767e079
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

In order to avoid unexpected traps into EL3/MON mode, this patch
resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64,
and SDCR and HDCR for AArch32.

MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the
start of BL1 and BL31/SMP_MIN.

For MDCR_EL2/HDCR, this patch zero's the bits that are
architecturally UNKNOWN values on reset. This is done when
exiting from EL3/MON mode but only on platforms that support
EL2/HYP mode but choose to exit to EL1/SVC mode.

Fixes ARM-software/tf-issues#430

Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6
Signed-off-by: David Cunado <david.cunado@arm.com>

readme.md: Add tested Linaro release information for FVPs

The platform testing information in the readme currently states which
Linaro release has been tested on Juno platform.

This patch adds the same information for the AArch64/32 FVPs platforms.

Change-Id: Ifa89843ee1744e5030367197648b7a2f4c44cc24
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

This patch adds the secure payload dispatcher for interacting
with Google's Trusty TEE. Documentation for Trusty can be found
at https://source.android.com/security/trusty



Original authors:
-----------------
* Arve Hjønnevåg <arve@android.com>
* Michael Ryleev <gmar@google.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

rk3399: fixes and updates for s2r

Alphabetical reordering for build options and make files

RK3399 M0 build system improvements

When build variables are assigned or processed en masse, they'd appear
neater in alphabetical order.

Static initializations are moved to a separate file,
make_helpers/defaults.mk, which in itself is sorted alphabetically.

No functional changes.

Change-Id: I966010042b33de6b67592fb9ffcef8fc44d7d128
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

At present, build options in the user guide aren't listed in any
specific order. Ordering them alphabetically is a standard practice, and
is also easier on the reader.

Contents unchanged.

Change-Id: Ibc36f3a2a576edb86c1a402430d2ef5adcb2f144
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

We have do something for clocks gate.

Fox example as the below:
susped:
clk_gate_con_save();
clk_gate_con_disable();

resume:
clk_gate_con_restore();
--

SO, add the plls_suspend_prepare() and plls_resume_finish() are not
necessary to S2R, that will save S2R time if remove them.

BRANCH=none
BUG=chrome-os-partner:58870,chrome-os-partner:55934
TEST=build kevin, two dogfooders with suspend_stress_test
passing 3000 cycles and still going on.

Change-Id: Icfbabc0b3ea8d2b5108d4f3de99a803b6d459669
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of
it because the kernel can't touch SGRF.

Basically the WDT didn't stop at suspend time, it just switched from the
24M to the 32k clock. That meant that the WDT would fire if you slept for
long enough. In other word, the watchdog timer over count will increase to
750 (24*1000/32) times.
The RK3399 HW watchdog interval is 21 seconds. When machine enters the
suspend, the watchdog will reset the system after 35.7 (750/21) hours.

BUG=chrome-os-partner:59257
TEST=daisydog checked and set value, powerd_dbus_suspend to verify.

Change-Id: I88bb2a05b7d67d5ffd292f9d05d033ae9a6a3593
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

This patch adds dependency rule generation and inclusion to the M0
Makefile, so that M0 objects will get correctly remade with an
incremental build if a header file they included changed.

Change-Id: I2067bd9fd4d9dad3e77a09cbf09c7b4db3c1eda5
Signed-off-by: Julius Werner <jwerner@chromium.org>

The dependencies in the M0 Makefile are not correctly laid out, which
may lead to errors with make -j if the binary target gets evaluated
before the target that creates the directory. In addition, the M0
Makefile just calls mkdir without using the platform-independent macros
from the main ARM TF build system. This patch fixes those issues,
removes some unused (and broken) M0 build targets and merges the two M0
output directories into one (since there's no real point splitting it up
and it creates more hassle).

Change-Id: Ia5002479cf9c57fea7aefa8ca88e373df3a51f61
Signed-off-by: Julius Werner <jwerner@chromium.org>

Porting guide: Improve bl1_plat_mem_check() doc

BL31 runtime instrumentation fixes and documentation update

This patch fixes the type of the return value of bl1_plat_mem_check()
in the porting guide. It also specifies the expected return value.

Change-Id: I7c437342b8bfb1e621d74b2edf0aaf97b913216a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Without an explicit cache flush, the next timestamp captured might have
a bogus value.

This can happen if the following operations happen in order,
on a CPU that's being powered down.

1) ENTER PSCI timestamp is captured with caches enabled.

2) The next timestamp (ENTER_HW_LOW_PWR) is captured with caches
   disabled.

3) On a system that uses a write-back cache configuration, the
   cache line that holds the PMF timestamps is evicted.

After step 1), the ENTER_PSCI timestamp is cached and not in main memory.
After step 2), the ENTER_HW_LOW_PWR timestamp is stored in main memory.
Before the CPU power down happens, the hardware evicts the cache line that
contains the PMF timestamps for this service.  As a result, the timestamp
captured in step 2) is overwritten with a bogus value.

Change-Id: Ic1bd816498d1a6d4dc16540208ed3a5efe43f529
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Change-Id: I8e50df67e860b9589834445761a7b9927690fdce
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Support rk3399 dram

Fix format of patches passed to checkpatch