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  1. 28 Jun, 2021 1 commit
  3. 16 Jun, 2021 1 commit
  5. 05 May, 2021 1 commit
    • Andre Przywara's avatar
      fix(plat/arm_fpga): increase initrd size · c3ce73be
      Andre Przywara authored 
      

In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.

As initrds are the most common and easy userland option for the boards,
let's increase the maximum size to the advertised 100 MB, to avoid
unpacking errors when an initrd exceeds the current limit of 20 MB.

Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      c3ce73be
  7. 30 Apr, 2021 1 commit
  9. 27 Apr, 2021 1 commit
  11. 21 Apr, 2021 5 commits
    • Grzegorz Szymaszek's avatar
      fdts: stm32mp1: add support for the Seeed Odyssey SoM and board · c3c6732f
      Grzegorz Szymaszek authored 
      

Seeed Studio’s SoM‐STM32MP157C is a System‐on‐Module that integrates the
STM32MP157C MPU (the 650 MHz dual‐core variant with a GPU and a
cryptographic processor) the STPMIC1A PMIC, 512 MB of DDR3 RAM and a
4 GB eMMC. There are two LEDs as well, one hardwired to the PMIC’s VDD
output, and the other available at the MPU’s port PG3. The SoM can be
plugged into a carrier board using its three 70‑pin connectors.

Seeed Odyssey‐STM32MP157C is the reference carrier board for the SoM in
a Raspberry Pi‐like form factor. It features a WiFi/Bluetooth chip, a
microSD card port and various I/O interfaces.

The device tree is based on the DKx boards. TF‑A was successfully tested
on the board with Buildroot 2021.02 and U-Boot 2021.04.
Signed-off-by: default avatarGrzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: I2c9aecc925561e8d338dddbb192d3bb23a533914
      c3c6732f
    • Grzegorz Szymaszek's avatar
      fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl · 0e480e0e
      Grzegorz Szymaszek authored 
      

The new pins—PA8, PA9, PE5, and PC7—are described in a new pinctrl node
named “sdmmc2-d47-3”, AKA phandle “sdmmc2_d47_pins_d”. These names are
identical to their Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: default avatarGrzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ie6a019f4361790f6b5d4910ce1e7b507a6c6a21a
      0e480e0e
    • Grzegorz Szymaszek's avatar
      fdts: stm32mp1: add I2C2 pins in the pinctrl · 214b4f9a
      Grzegorz Szymaszek authored 
      

Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.

The pins used, PH4 and PH5, are described in a new pinctrl node named
“i2c2-0”, AKA phandle “i2c2_pins_a”. These names are identical to their
Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: default avatarGrzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ief6f0a632cfa992dcf3fed95d266ad6a07a96fe0
      214b4f9a
    • Grzegorz Szymaszek's avatar
      fdts: stm32mp1: add the I2C2 peripheral in the SoC DTS · 3ef2208b
      Grzegorz Szymaszek authored 
      

Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.
Signed-off-by: default avatarGrzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Iec9c80f29ce95496e8f1b079b7a23f1914b74901
      3ef2208b
    • Alexei Fedorov's avatar
      Plat FVP: Fix Generic Timer interrupt types · dfa6c540
      Alexei Fedorov authored 
      

The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:

Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."

Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."

The following files in fdts\

fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts

describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:

interrupts = <1 13 0xff01>,
             <1 14 0xff01>,
             <1 11 0xff01>,
             <1 10 0xff01>;

, see include\dt-bindings\interrupt-controller\arm-gic.h:

which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware

This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.

Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      dfa6c540
  13. 20 Apr, 2021 2 commits
    • Mikael Olsson's avatar
      Add SiP service to configure Arm Ethos-N NPU · 76a21174
      Mikael Olsson authored 
      

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.

Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.
Signed-off-by: default avatarMikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
      76a21174
    • Mikael Olsson's avatar
      plat/arm/juno: Add support to use hw_config in BL31 · 5d5fb10f
      Mikael Olsson authored 
      

To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.

Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.
Signed-off-by: default avatarMikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
      5d5fb10f
  15. 14 Apr, 2021 1 commit
  17. 02 Mar, 2021 1 commit
  19. 09 Feb, 2021 1 commit
  21. 03 Feb, 2021 1 commit
  23. 27 Jan, 2021 1 commit
  25. 19 Jan, 2021 1 commit
    • Ahmad Fatoum's avatar
      fdts: stm32mp1: add support for Linux Automation MC-1 board · 2fbb6064
      Ahmad Fatoum authored 
      

The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.

The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.

This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.

Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: default avatarAhmad Fatoum <a.fatoum@pengutronix.de>
      2fbb6064
  27. 14 Dec, 2020 2 commits
  29. 08 Dec, 2020 2 commits
  31. 23 Nov, 2020 2 commits
  33. 20 Oct, 2020 1 commit
  35. 13 Oct, 2020 1 commit
  37. 12 Oct, 2020 1 commit
  39. 08 Oct, 2020 1 commit
  41. 29 Sep, 2020 1 commit
    • Andre Przywara's avatar
      arm_fpga: Add devicetree file · b48883c7
      Andre Przywara authored 
      

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b48883c7
  43. 28 Sep, 2020 1 commit
  45. 24 Sep, 2020 1 commit
    • Yann Gautier's avatar
      fdts: stm32mp1: realign device tree with kernel · 277d6af5
      Yann Gautier authored 
      

There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A

The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.

There are 4 packages available, for which  the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.

STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.

Some reordering is done in other files, and realign with kernel DT files.

The DDR files are generated with our internal tool, no changes in the
registers values.

Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      277d6af5
  47. 22 Sep, 2020 1 commit
  49. 16 Sep, 2020 1 commit
  51. 08 Sep, 2020 1 commit
  53. 07 Sep, 2020 1 commit
  55. 28 Aug, 2020 1 commit
  57. 27 Aug, 2020 2 commits
  59. 31 Jul, 2020 1 commit
    • Manish Pandey's avatar
      tbbr/dualroot: rename SP package certificate file · 03a5225c
      Manish Pandey authored 
      

Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.

SP_CONTENT_CERT_ID is the certificate file which is currently generated
and signed with trusted world key which in-turn is derived from Silicon
provider RoT key.
To allow dual signing domain for SP packages, other certificate file
will be derived from Platform owned RoT key.

This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
does other related changes.
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
      03a5225c
  61. 30 Jul, 2020 1 commit