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  1. 08 Aug, 2020 1 commit
    • johpow01's avatar
      MISRA cleanup in mem_region and semihosting files · 633fa4cd
      johpow01 authored 
      

MISRA defect cleanup and general code cleanup in mem_region.c and
semihosting.c.  This task also called for cleanup of the ARM NOR flash
driver but that was removed at some point since the Jira task was
created.  This patch fixes all MISRA defects in these files except for a
few "Calling function "console_flush()" which returns error information
without testing the error information." errors which can't really be
avoided.

Defects Fixed

File                           Line Rule
lib/semihosting/semihosting.c  70   MISRA C-2012 Rule 14.4 (required)
lib/semihosting/semihosting.c  197  MISRA C-2012 Rule 14.3 (required)
lib/semihosting/semihosting.c  210  MISRA C-2012 Rule 14.4 (required)
lib/utils/mem_region.c         128  MISRA C-2012 Rule 12.1 (advisory)
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: I21a039d1cfccd6aa4301da09daec15e373305a80
      633fa4cd
  3. 23 Jul, 2020 3 commits
  5. 21 Jul, 2020 1 commit
  7. 27 Jun, 2020 1 commit
  9. 25 Jun, 2020 3 commits
  11. 24 Jun, 2020 5 commits
  13. 22 Jun, 2020 2 commits
  15. 12 Jun, 2020 2 commits
  17. 09 Jun, 2020 1 commit
    • Varun Wadekar's avatar
      cpus: denver: disable cycle counter when event counting is prohibited · c5c1af0d
      Varun Wadekar authored 
      

The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the
PMCR_EL0 to be saved in non-secure context.

This patch disables cycle counter when event counting is prohibited
immediately on entering the secure world to avoid leaking useful
information about the PMU counters. The context saving code later
saves the value of PMCR_EL0 to the non-secure world context.

Verified with 'PMU Leakage' test suite.

 ******************************* Summary *******************************
 > Test suite 'PMU Leakage'
                                                                 Passed
 =================================
 Tests Skipped : 2
 Tests Passed  : 2
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 4
 =================================
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875
      c5c1af0d
  19. 08 Jun, 2020 1 commit
    • Manish Pandey's avatar
      cert_create: add SiP owned secure partitions support · 0792dd7d
      Manish Pandey authored 
      

Add support to generate certificate "sip-sp-cert" for Secure
Partitions(SP) owned by Silicon provider(SiP).
To avoid deviation from TBBR specification the support is only added for
dualroot CoT and not for TBBR CoT.

A single certificate file is generated containing hash of individual
packages. Maximum 8 secure partitions are supported.

Following new options added to cert_tool:
 --sip-sp-cert --> SiP owned Secure Partition Content Certificate
 --sp-pkg1 --> Secure Partition Package1 file
 --sp-pkg2
 .....
 --sp-pkg8

Trusted world key pair is used for signing.

Going forward, this feature can be extended for Platfrom owned
Partitions, if required.
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ia6dfbc1447cfb41b1fcbd12cf2bf7b88f409bd8d
      0792dd7d
  21. 02 Jun, 2020 2 commits
    • Jimmy Brisson's avatar
      Enable ARMv8.6-ECV Self-Synch when booting to EL2 · 29d0ee54
      Jimmy Brisson authored 
      

Enhanced Counter Virtualization, ECV, is an architecture extension introduced
in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the
control register to enable this extension when booting a hypervisor at EL2.

Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      29d0ee54
    • Jimmy Brisson's avatar
      Enable ARMv8.6-FGT when booting to EL2 · 110ee433
      Jimmy Brisson authored 
      

The Fine Grained Traps (FGT) architecture extension was added to aarch64 in
ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific
instructions in a more fine grained manner, with an enable bit for each
instruction. This patch adds support for this extension by enabling the
extension when booting an hypervisor at EL2.

Change-Id: Idb9013ed118b6a1b7b76287237096de992ca4da3
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      110ee433
  23. 01 Jun, 2020 2 commits
  25. 26 May, 2020 1 commit
  27. 19 May, 2020 2 commits
    • johpow01's avatar
      Enable v8.6 WFE trap delays · 6cac724d
      johpow01 authored 
      

This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.

The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d
      6cac724d
    • Max Shvetsov's avatar
      Fix exception in save/restore of EL2 registers. · 30ee3755
      Max Shvetsov authored 
      

Removing FPEXC32_EL2 from the register save/restore routine for EL2
registers since it is already a part of save/restore routine for
fpregs.
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I5ed45fdbf7c8efa8dcfcd96586328d4f6b256bc4
      30ee3755
  29. 14 May, 2020 1 commit
    • Manish V Badarkhe's avatar
      Implement workaround for AT speculative behaviour · 45aecff0
      Manish V Badarkhe authored 
      During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instruction using out-of-context
translation regime.

Workaround is implemented as below during EL's (EL1 or EL2)
"context_restore" operation:
1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1
   bits for EL1 or EL2 (stage1 and stage2 disabled)
2. Save all system registers except TCR and SCTLR (for EL1 and EL2)
3. Do memory barrier operation (isb) to ensure all
   system register writes are done.
4. Restore TCR and SCTLR registers (for EL1 and EL2)

Errata details are available for various CPUs as below:
Cortex-A76: 1165522
Cortex-A72: 1319367
Cortex-A57: 1319537
Cortex-A55: 1530923
Cortex-A53: 1530924

More details can be found in mail-chain:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html



Currently, Workaround is implemented as build option which is default
disabled.
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0
      45aecff0
  31. 30 Apr, 2020 1 commit
  33. 29 Apr, 2020 1 commit
    • Andre Przywara's avatar
      fdt/wrappers: Replace fdtw_read_cells() implementation · ff4e6c35
      Andre Przywara authored 
      Our fdtw_read_cells() implementation goes to great lengths to
sanity-check every parameter and result, but leaves a big hole open:
The size of the storage the value pointer points at needs to match the
number of cells given. This can't be easily checked at compile time,
since we lose the size information by using a void pointer.
Regardless the current usage of this function is somewhat wrong anyways,
since we use it on single-element, fixed-length properties only, for
which the DT binding specifies the size.
Typically we use those functions dealing with a number of cells in DT
context to deal with *dynamically* sized properties, which depend on
other properties (#size-cells, #clock-cells, ...), to specify the number
of cells needed.

Another problem with the current implementation is the use of
ambiguously sized types (uintptr_t, size_t) together with a certain
expectation about their size. In general there is no relation between
the length of a DT property and the bitness of the code that parses the
DTB: AArch64 code could encounter 32-bit addresses (where the physical
address space is limited to 4GB [1]), while AArch32 code could read
64-bit sized properties (/memory nodes on LPAE systems, [2]).

To make this more clear, fix the potential issues and also align more
with other DT users (Linux and U-Boot), introduce functions to explicitly
read uint32 and uint64 properties. As the other DT consumers, we do this
based on the generic "read array" function.
Convert all users to use either of those two new functions, and make
sure we never use a pointer to anything other than uint32_t or uint64_t
variables directly.

This reveals (and fixes) a bug in plat_spmd_manifest.c, where we write
4 bytes into a uint16_t variable (passed via a void pointer).

Also we change the implementation of the function to better align with
other libfdt users, by using the right types (fdt32_t) and common
variable names (*prop, prop_names).

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi#n874
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/ecx-2000.dts



Change-Id: I718de960515117ac7a3331a1b177d2ec224a3890
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      ff4e6c35
  35. 07 Apr, 2020 2 commits
    • Julius Werner's avatar
      coreboot: Add memory range parsing · 579d1e90
      Julius Werner authored 
      

This patch adds code to parse memory range information passed by
coreboot, and a simple helper to test whether a specific address belongs
to a range. This may be useful for coreboot-using platforms that need to
know information about the system's memory layout (e.g. to check whether
an address passed in via SMC targets valid DRAM).
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
      579d1e90
    • Masahiro Yamada's avatar
      locks: bakery: use is_dcache_enabled() helper · 11504163
      Masahiro Yamada authored 
      

bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3)
to check whether the dcache is enabled.

Using is_dcache_enabled() is cleaner, and a good abstraction for
the library code like this.

A problem is is_dcache_enabled() is declared in the local header,
lib/xlat_tables_v2/xlat_tables_private.h

I searched for a good place to declare this helper. Moving it to
arch_helpers.h, closed to cache operation helpers, looks good enough
to me.

I also changed the type of 'is_cached' to bool for consistency,
and to avoid MISRA warnings.

Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      11504163
  37. 03 Apr, 2020 2 commits
    • Pramod Kumar's avatar
      xlat lib v2: Add support to pass shareability attribute for normal memory region · 06aca857
      Pramod Kumar authored 
      

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. it defaults to inner shareability.

There are platforms where memories (like SRAM) are not placed at snoopable
region in advaned interconnect like CCN/CMN hence snoopable transaction is
not possible to these memory. Though These memories could be mapped in MMU
as MT_NON_CACHEABLE, data caches benefits won't be available.

If these memories are mapped as cacheable with non-shareable attribute,
when only one core is running like at boot time, MMU data cached could be
used for faster execution. Hence adding support to pass the shareability
attribute for memory regions.
Signed-off-by: default avatarPramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754
      06aca857
    • Masahiro Yamada's avatar
      xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled() · 3cde15fa
      Masahiro Yamada authored 
      

Using get_current_el_maybe_constant() produces more optimized code
because in most cases, we know the exception level at build-time.
For example, BL31 runs at EL3, so unneeded code will be trimmed.

[before]

0000000000000000 <is_dcache_enabled>:
   0:   d5384240        mrs     x0, currentel
   4:   53020c00        ubfx    w0, w0, #2, #2
   8:   7100041f        cmp     w0, #0x1
   c:   54000081        b.ne    1c <is_dcache_enabled+0x1c>  // b.any
  10:   d5381000        mrs     x0, sctlr_el1
  14:   53020800        ubfx    w0, w0, #2, #1
  18:   d65f03c0        ret
  1c:   7100081f        cmp     w0, #0x2
  20:   54000061        b.ne    2c <is_dcache_enabled+0x2c>  // b.any
  24:   d53c1000        mrs     x0, sctlr_el2
  28:   17fffffb        b       14 <is_dcache_enabled+0x14>
  2c:   d53e1000        mrs     x0, sctlr_el3
  30:   17fffff9        b       14 <is_dcache_enabled+0x14>

[after]

0000000000000000 <is_dcache_enabled>:
   0:   d53e1000        mrs     x0, sctlr_el3
   4:   53020800        ubfx    w0, w0, #2, #1
   8:   d65f03c0        ret

Change-Id: I3698fae9b517022ff9fbfd4cad3a320c6e137e10
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      3cde15fa
  39. 02 Apr, 2020 1 commit
    • Masahiro Yamada's avatar
      xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES · 268131c2
      Masahiro Yamada authored 
      

If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the
.rodata section instead of .bss section.

This causes a warning like:

/tmp/ccswitLr.s: Assembler messages:
/tmp/ccswitLr.s:297: Warning: setting incorrect section attributes for .rodata

It is practically no problem, but I want to keep the build log clean.

Put the base table into the "base_xlat_table" section to suppress the
assembler warnings.

The linker script determines its final destination; rodata section if
PLAT_RO_XLAT_TABLES=1, or bss section otherwise. So, the result is the
same.

Change-Id: Ic85d1d2dddd9b5339289fc2378cbcb21dd7db02e
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      268131c2
  41. 31 Mar, 2020 2 commits
    • Masahiro Yamada's avatar
      fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCES · c452ba15
      Masahiro Yamada authored 
      

fconf_dyn_cfg_getter.c calls FCONF_REGISTER_POPULATOR(), which populates
the fconf_populator structure.

However, bl1/bl1.ld.S does not have:

        __FCONF_POPULATOR_START__ = .;
        KEEP(*(.fconf_populator))
        __FCONF_POPULATOR_END__ = .;

So, this is not linked to bl1.elf

We could change either bl1/bl1.lds.S or lib/fconf/fconf.mk to make
them consistent.

I chose to fix up fconf.mk to keep the current behavior.

This is a groundwork to factor out the common code from linker scripts.

Change-Id: I07b7ad4db4ec77b57acf1588fffd0b06306d7293
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      c452ba15
    • Masahiro Yamada's avatar
      xlat_tables_v2: add enable_mmu() · f5547735
      Masahiro Yamada authored 
      

enable_mmu_* has a different function name, so it is not handy in the
shared code. enable_mmu() calls an appropriate one depending on the
exception level.

Change-Id: I0657968bfcb91c32733f75f9259f550a5c35b1c3
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      f5547735
  43. 27 Mar, 2020 1 commit
  45. 20 Mar, 2020 1 commit
  47. 16 Mar, 2020 1 commit
    • Louis Mayencourt's avatar
      fconf: Clean Arm IO · a6de824f
      Louis Mayencourt authored 
      

Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
removes the duplicate io_policies and functions definition.

This patch:
- replace arm_io_storage.c with the content of arm_fconf_io_storage.c
- rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB.
- use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb.
- propagate DEFINES when parsing dts.
- use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb.
- set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior
  of fvp stays the same as it was before the introduction of fconf.

Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      a6de824f