- 31 Jan, 2020 6 commits
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Varun Wadekar authored
This patch fixes violations for the following MISRA rules * Rule 5.7 "A tag name shall be a unique identifier" * Rule 10.1 "Operands shall not be of an inappropriate essential type" * Rule 10.3 "The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category" * Rule 10.4 "Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category" * Rule 20.7 "Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses" * Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The PMC driver is used only by Tegra210 and Tegra132 platforms. This patch removes pmc.c from the common makefile and moves it to the platform specific makefiles. As a result, the PMC code from common code has been moved to Tegra132 and Tegra210 platform ports. Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes the per-platform, weakly defined TZDRAM setup handler, as all affected platforms implement the actual handler. Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes the weakly defined per-platform SiP handler as all platforms implement this handler, defeating the need for a weak definition. Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes all the weakly defined PSCI handlers defined per-platform, to improve code coverage numbers and reduce MISRA defects. Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch converts the weakly defined platform setup handlers into actual platform specific handlers to improve code coverage numbers and some MISRA defects. The weakly defined handlers never get executed thus resulting in lower coverage - function, function calls, statements, branches and pairs. Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 23 Jan, 2020 1 commit
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Varun Wadekar authored
This patch fixes the header file paths to include debug.h from the right location. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b
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- 18 Dec, 2019 1 commit
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Varun Wadekar authored
This patch saves the boot parameters provided by the previous bootloader during cold boot and passes them to Trusty. Commit 06ff251e introduced the plat_trusty_set_boot_args() handler, but did not consider the boot parameters passed by the previous bootloader. This patch fixes that anomaly. Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 17 Dec, 2019 1 commit
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Varun Wadekar authored
This patch enables per-CPU GIC CPU interfaces during CPU power on. The previous code initialized the distributor for all CPUs, which was not required. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8
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- 28 Nov, 2019 1 commit
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Varun Wadekar authored
This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Oct, 2019 1 commit
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Vignesh Radhakrishnan authored
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e Fake system suspend relies on software running on EL3 to trigger a warm reset. Revert enabling fake system suspend, as the software running on El3 is not allowed to trigger a warm reset. Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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- 05 Sep, 2019 1 commit
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Varun Wadekar authored
This patch fixes a coding error, where the size of the protected memory area was truncated due to an incorrect typecast. This defect was found by coverity and reported as CID 336781. Change-Id: I41878b0a9a5e5cd78ef3393fdc7b9ea7f7403ed3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 15 Aug, 2019 1 commit
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Ambroise Vincent authored
This patch updates all Tegra platforms to use the new multi console API. Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 20 Jun, 2019 2 commits
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Andreas Färber authored
initilise -> initialise Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: Ib129e6bd48623b6565b669bc674208893a2f7668
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Andreas Färber authored
Let bl31_check_ns_address() print the address it doesn't like. Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: I29a4fb33c24e9f7464ccd2ea44a4608f5cfe5be6
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- 03 Apr, 2019 1 commit
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Ambroise Vincent authored
Now it is needed to use the full path of the common header files. Commit 09d40e0e ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 01 Mar, 2019 1 commit
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Varun Wadekar authored
This patch provides dummy macros and platform files to compile the io_storage driver backend. This patch is necessary to remove the "--unresolved=el3_panic" linker flag from Tegra's makefiles and allow us to revert this workaround, previously suggested by the ARM toolchain team. The "--unresolved=el3_panic" flag actually was a big hammer that allowed Tegra platforms to work with armlink previously but it masks legit errors with the code as well. Change-Id: I0421d35657823215229f84231896b84167f90548 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 05 Feb, 2019 3 commits
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Varun Wadekar authored
This patch initilises the per-CPU GIC bits during cold boot and secondary CPU power up. Commit 80c50eea accidentally left out this part. Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch udpates the SPE console driver to prepend '\r' to '\n'. This fixes the alignment of prints seen by the host machines on their UART ports. Tested by collecting the logs from host PC using Cutecom Reported by: Mustafa Bilgen <mbilgen@nvidia.com> Change-Id: I6e0b412bd71ff5eb889582071df8c157da5175ed Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Vignesh Radhakrishnan authored
As per ARM ARM D1.17.2, any physical IRQ interrupt received by the PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1', irrespective of the value of the PSTATE.I bit value. This patch programs the SCR_EL3.IRQ bit before entering CPU standby state, to allow an IRQ to wake the PE. On waking up, the previous SCR_EL3 value is restored. Change-Id: Ie81cf3a7668f5ac35f4bf2ecc461b91b9b60650c Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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- 31 Jan, 2019 14 commits
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Varun Wadekar authored
This patch updates the state machine to "not present" if the bpmp firmware is not found in the system during boot. The suspend handler also checks now if the interface exists, before updating the internal state machine. Reported by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: If8fd7f8e412bb603944555c24826855226e7f48c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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kalyani chidambaram authored
This patch clears the PMC's DPD registers on resuming from System Suspend, for all Tegra210 platforms that support the sc7entry-fw. Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305 Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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Varun Wadekar authored
This patch adds suspend and resume handlers for the BPMP interface. Mark the interface as "suspended" before entering System Suspend and verify that BPMP is alive on exit. Change-Id: I74ccbc86125079b46d06360fc4c7e8a5acfbdfb2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no longer be supported on Tegra210 platforms and its functionality will be divided across the CPU and sc7entry-fw. The sc7entry-fw takes care of performing the hardware sequence required to enter System Suspend (SC7 power state) from the COP. The CPU is required to load this firmware to the internal RAM of the COP and start the sequence. The CPU also make sure that the COP is off after cold boot and is only powered on when we want to start the actual System Suspend sequence. The previous bootloader loads the firmware to TZDRAM and passes its base and size as part of the boot parameters. The EL3 layer is supposed to sanitize the parameters before touching the firmware blob. To assist the warmboot code with the PMIC discovery, EL3 is also supposed to program PMC's scratch register #210, with appropriate values. Without these settings the warmboot code wont be able to get the device out of System Suspend. Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a helper function to find the last standing CPU in a cluster. Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch organizes the memory and mmio maps linearly, to make the mmap_add_region process faster. The microsecond timer has been moved to individual platforms instead of making it a common step, as it further speeds up the memory map creation process. Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds helper functions to help platforms with cluster state entry and exit decisions. * tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate * tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate * tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU? Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes the error print displayed when bpmp init fails. On platforms that do not load the bpmp firmware, this print is seen on every cluster idle and powerdown request, cluttering the logs. Change-Id: I9e30007a913080406052fc32d5360ff70a019d75 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to handle secure PPIs for Tegra watchdog timers. This functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING configuration variable and is only enabled for Tegra210 platforms, for now. Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt is not direclty wired to the GICD. It goes to the flow controller instead, for power state management. But the flow controller can route the FIQ to the GICD, as a PPI, which can then get routed to the target CPU. This patch adds routines to enable/disable routing the legacy FIQ used by the watchdog timers, to the GICD. Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Jeetesh Burman authored
Whenever the VPR memory is resized, the GPU is put into reset first and then the new VPR parameters are programmed to the memory controller block. There exists a scenario, where the GPU might be out before we program the new VPR parameters. This means, the GPU would still be using older settings and leak secrets. This patch puts the GPU back into reset, if it is out of reset after resizing VPR, to mitigate this hole. Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931 Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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Varun Wadekar authored
This patch updates the secure interrupt handler to mark the interrupt as complete in case the NS world has not registered a handler. Change-Id: Iebe952305f7db46375303699b6150611439475df Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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steven kao authored
This patch adds support to the bpmp_ipc driver to allow clients to enable/disable clocks to hardware blocks. Currently, the API only supports SE devices. Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90 Signed-off-by: steven kao <skao@nvidia.com>
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Varun Wadekar authored
This patch adds a default implementation for the platform specific CPU standby power handler. Tegra SoCs can override this handler with their own implementations. Change-Id: I91e513842f194b1e2b1defa2d833bb4d9df5f06b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Jan, 2019 5 commits
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Varun Wadekar authored
This patch removes the usage of this platform config, as it is always enabled by all the supported platforms. Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Dilan Lee authored
This patch adds a platform setup handler that gets called after the MMU is enabled. Platforms wanting to make use of this handler should declare 'plat_late_platform_setup' handler in their platform files, to override the default weakly defined handler. Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c Signed-off-by: Dilan Lee <dilee@nvidia.com>
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Varun Wadekar authored
There are Tegra platforms which have limited UART ports and so all the components have to share the console. The SPE helps out by collecting all the logs in such cases and prints them on the shared UART port. This patch adds a driver to communicate with the SPE driver, which in turn provides the console. Change-Id: Ie750520b936b8bed0ab1d876f03fc0a3490a85a3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch includes the console driver from individual platform makefiles and removes it from tegra_common.mk. This allows future platforms to include consoles of their choice. Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF. This patch changes the search criteria, to look for this marker, to calculate the size of the saved context. Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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