- 19 Jan, 2021 3 commits
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Graeme Gregory authored
This allows PSCI in TF-A to signal platform power states to QEMU via a controller in secure space. This required a sbsa-ref specific version of PSCI functions for the platform. Also adjusted the MMU range to also include the new EC. Add a new MMU region for the embedded controller and increase the size of xlat tables by one for the new region. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee
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Graeme Gregory authored
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512 cores in upto 64 clusters. Implement a qemu_sbsa specific topology file and increase the BL31_SIZE to accommodate the bigger table sizes. Change platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so plat_helpers.S calculates correct result. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
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Graeme Gregory authored
Rather than re-create this file in multiple qemu variants instead caclulate the shift needed to convert MPIDR to position. Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h for both qemu and qemu_sbsa to enable this calculation. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
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- 13 Jan, 2021 1 commit
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Masahisa Kojima authored
This implements support for UEFI secure variable storage using standalone MM framework on qemu_sbsa platform. Non-secure shared memory between UEFI and standalone MM is allocated at the top of DRAM. DRAM size of qemu_sbsa varies depends on the QEMU parameter, so the non-secure shared memory is allocated by trusted firmware and passed the base address and size to UEFI through device tree "/reserved-memory" node. Change-Id: I367191f408eb9850b7ec7761ee346b014c539767 Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 01 Dec, 2020 1 commit
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Masato Fukumori authored
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB. sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If qemu is configured with 512 cpus, region size used by qemu is greater than 4KB. Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org> Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
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- 18 Aug, 2020 1 commit
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Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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- 03 Jun, 2020 1 commit
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Masahisa Kojima authored
64KB was not enouth to handle fdt, bl2 shows following error message. "ERROR: Invalid Device Tree at 0x10000000000: error -3" This patch increases the size to 1MB to address above error. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I0726a0cea95087175451da0dba7410acd27df808
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259
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- 01 Oct, 2019 2 commits
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Radoslaw Biernacki authored
This patch adds mapping for secure FLASH0 for qemu/virt and qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both platforms share common code, changes in common defines was necessary. For qemu_sbsa, this patch adds necessary mapping in order to boot without semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with variables) since it need to "run in place" in non secure domain. Changes for this are under RFC at edk2-platforms mailing list: https://patches.linaro.org/patch/171327/ (edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc). In docs qemu/virt is described as using semi-hosting, therefore this change should be orthogonal to existing assumptions while giving possibility to store both bl1 and fip in FLASH0 at some point (additional changes required for that). Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
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Radoslaw Biernacki authored
This patch introduces Qemu SBSA platform. Both platform specific files where copied from qemu/qemu with changes for DRAM base above 32bit and removal of ARMv7 conditional defines/code. Documentation is aligned to rest of SBSA patches along the series and planed changes in edk2-platform repo. Fixes ARM-software/tf-issues#602 Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
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