1. 20 Apr, 2021 6 commits
  2. 19 Apr, 2021 2 commits
  3. 16 Apr, 2021 1 commit
  4. 15 Apr, 2021 1 commit
  5. 14 Apr, 2021 3 commits
  6. 13 Apr, 2021 2 commits
  7. 12 Apr, 2021 4 commits
  8. 09 Apr, 2021 1 commit
    • Manish Pandey's avatar
      plat/arm: don't provide NT_FW_CONFIG when booting hafnium · 2b6fc535
      Manish Pandey authored
      
      
      NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
      BL33, fvp platforms use this to pass measured boot configuration and
      the x0 register is used to pass the base address of it.
      
      In case of hafnium used as hypervisor in normal world, hypervisor
      manifest is expected to be passed from BL31 and its base address is
      passed in x0 register.
      
      As only one of NT_FW_CONFIG or hypervisor manifest base address can be
      passed in x0 register and also measured boot is not required for SPM so
      disable passing NT_FW_CONFIG.
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e
      2b6fc535
  9. 08 Apr, 2021 9 commits
  10. 07 Apr, 2021 7 commits
  11. 06 Apr, 2021 4 commits
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization · 40d08192
      Pali Rohár authored
      
      
      Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
      Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
      Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
      mode. Set this bit.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
      40d08192
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call · ccec1bd5
      Pali Rohár authored
      
      
      The third argument of the reg_set() function has name 'mask', which
      indicates that it is a mask applied to the register value which is
      going to be updated. But the implementation of this function uses
      this argument to clear prior value of the register, i.e. instead of
        new_val = (old_val & ~mask) | (data & mask);
      it does
        new_val = (new_val & ~mask) | data;
      
      (The more proper name for this function should be reg_clrsetbits(),
       since internally it calls mmio_clrsetbits_32().)
      
      To make code more readable set 'mask' argument to real mask, i.e. bits
      of register values which are going to be updated.
      
      This patch does not make any functional change, only cosmetic, due to
      how 'mask' is interpreted.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
      ccec1bd5
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Fix configuring polarity invert bits · ee4c70eb
      Pali Rohár authored
      
      
      TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
      appropriate polarity is inverted. Otherwise these bits should be
      cleared.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
      ee4c70eb
    • Heyi Guo's avatar
      plat/arm/arm_image_load: refine plat_add_sp_images_load_info · abe6ce1d
      Heyi Guo authored
      
      
      Refine the function plat_add_sp_images_load_info() by saving the
      previous node and only setting its next link when the current node is
      valid. This can reduce the check for the next node and simply the
      total logic.
      Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
      Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88
      abe6ce1d