1. 28 May, 2021 1 commit
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation · 66a77528
      Pali Rohár authored
      
      
      UART parent clock is by default the platform's xtal clock, which is
      25 MHz.
      
      The value defined in the driver, though, is 25.8048 MHz. This is a hack
      for the suboptimal divisor calculation
        Divisor = UART clock / (16 * baudrate)
      which does not use rounding division, resulting in a suboptimal value
      for divisor if the correct parent clock rate was used.
      
      Change the code for divisor calculation to
        Divisor = Round(UART clock / (16 * baudrate))
      and change the parent clock rate value to 25 MHz.
      
      The final UART divisor for default baudrate 115200 is not affected by
      this change.
      
      (Note that the parent clock rate should not be defined via a macro,
      since the xtal clock can also be 40 MHz. This is outside of the scope of
      this fix, though.)
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
      66a77528
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