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  1. 10 Mar, 2021 1 commit
  3. 24 Feb, 2021 1 commit
  5. 12 Feb, 2021 1 commit
    • Pankaj Gupta's avatar
      nxp: added the makefile helper macros · b749ae3d
      Pankaj Gupta authored 
      

NXP specifc macro SET_NXP_MAKE_FLAG is added.

NXP has pool of multiple IPs. This macro helps:
- In soc.mk, this macro help the selected IP source files to be included
  for that SoC.
  -- The set of IPs required for one NXP SoC is different to the set of IPs
     required by another NXP SoC.

- For the same SoC,
  -- For one feature, the IP may be required in both BL2 and BL31.
  -- Without the above feature, that IP may be required in one.
     This macro help in selecting the inclusion of source and header files to:
     --- BL2 only
     --- BL31 only
     --- COMM (used by BL2 and BL31)
Signed-off-by: default avatarPankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cdb13b89aa815fc5219cf8bfb9666d0a9f78765
      b749ae3d
  7. 11 Feb, 2021 2 commits
    • Andre Przywara's avatar
      plat/arm: juno: Refactor juno_getentropy() · 543f0d8b
      Andre Przywara authored 
      

Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we will actually only ever request 16 bytes, as this is what
the hardware implements. Out of this, we only need at most 64 bits for
the canary.

In preparation for the introduction of the SMCCC TRNG interface, we
can simplify this Juno specific interface by making it compatible with
the generic one: We just deliver 64 bits of entropy on each call.
This reduces the complexity of the code. As the raw entropy register
readouts seem to be biased, it makes sense to do some conditioning
inside the juno_getentropy() function already.
Also initialise the TRNG hardware, if not already done.

Change-Id: I11b977ddc5417d52ac38709a9a7b61499eee481f
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      543f0d8b
    • Vijayenthiran Subramaniam's avatar
      plat/arm/rdn2: update TZC base address · 4e8060d2
      Vijayenthiran Subramaniam authored 
      

Update TZC base address to align with the recent changes in the platform
memory map.
Signed-off-by: default avatarVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a
      4e8060d2
  9. 09 Feb, 2021 2 commits
    • Manish V Badarkhe's avatar
      plat/arm: fvp: Protect GICR frames for fused/unused cores · f98630fb
      Manish V Badarkhe authored 
      

Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.

This opens up the security hole where the active core can write
the GICR frame of fused/inactive core. To avoid this issue, disable
the GICR frame of all inactive cores as below:

1. After primary CPU boots up, map GICR region of all cores as
   read-only.
2. After primary CPU boots up, map its GICR region as read-write
   and initialize its redistributor interface.
3. After secondary CPU boots up, map its GICR region as read-write
   and initialize its redistributor interface.
4. All unused/fused core's redistributor regions remain read-only and
   write attempt to such protected regions results in an exception.

As mentioned above, this patch offers only the GICR memory-mapped
region protection considering there is no facility at the GIC IP
level to avoid writing the redistributor area.

These changes are currently done in BL31 of Arm FVP and guarded under
the flag 'FVP_GICR_REGION_PROTECTION'.

As of now, this patch is tested manually as below:
1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core.
2. Verify data abort triggered by manually updating the ‘GICR_CTLR’
   register of core 1’s(fused) redistributor from core 0(active).

Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      f98630fb
    • Manish V Badarkhe's avatar
      plat/arm: fvp: Do not map GIC region in BL1 and BL2 · e0cea783
      Manish V Badarkhe authored 
      

GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memory regions in the
future.

Retains mapping of CCN interconnect region in BL1 and BL2
overlapped with the GIC memory region.

Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      e0cea783
  11. 08 Feb, 2021 1 commit
  13. 05 Feb, 2021 1 commit
  15. 03 Feb, 2021 1 commit
  17. 02 Feb, 2021 1 commit
  19. 29 Jan, 2021 13 commits
  21. 28 Jan, 2021 1 commit
  23. 24 Jan, 2021 4 commits
    • Samuel Holland's avatar
      allwinner: Leave CPU power alone during BL31 setup · ed267c92
      Samuel Holland authored 
      

Disabling secondary CPUs during boot is unnecessary because the other
CPUs are already in reset, and it saves an entirely insignificant amount
of power. Let's remove this bit of code that was added mostly "because
we can", and along with it remove an unconditional dependency on the CPU
ops functions.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7
      ed267c92
    • Samuel Holland's avatar
      allwinner: psci: Invert check in .validate_ns_entrypoint · 814dce8f
      Samuel Holland authored 
      

Checking the exceptional case and letting the success case fall through
is not only more idiomatic, but it also allows adding more exceptional
cases in the future, such as a check for overlapping secure DRAM.

Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      814dce8f
    • Samuel Holland's avatar
      allwinner: psci: Drop MPIDR check from .pwr_domain_on · 772ef7e7
      Samuel Holland authored 
      

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      772ef7e7
    • Samuel Holland's avatar
      allwinner: psci: Drop .get_node_hw_state callback · a1473c99
      Samuel Holland authored 
      

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary contract. First, the SCPI protocol has no way to represent
HW_STANDBY at the CPU power level. Second, the SCPI implementation
maintains its own logical view of power states, and its implementation
of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
Thus it cannot provide "the physical view of power state", as required
for this function by the PSCI specification.

Since the function is optional, drop it.

Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      a1473c99
  25. 22 Jan, 2021 1 commit
  27. 20 Jan, 2021 5 commits
    • Ming Huang's avatar
      plat/arm/css/sgi: Fix assert expression issue · 0301d09c
      Ming Huang authored 
      

Violation of MISRA-C Rule 14.4
Signed-off-by: default avatarMing Huang <huangming@linux.alibaba.com>
Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4
      0301d09c
    • Ming Huang's avatar
      plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue · 9feb1e2f
      Ming Huang authored 
      

The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and then crash.
sdei_dispatch_event() may return failing result in some cases,
for example kernel may not have registered a handler or RAS event
may happen early during boot. We restore the NS context when
sdei_dispatch_event() returns failing result.

error log :
Received delegated event
X0 :  0xC4000061
X1 :  0x0
X2 :  0x0
X3 :  0x0
Received event - 0xC4000061 on cpu 0
UnRecognized Event - 0xC4000061
Failed delegated event 0xC4000061, Status Invalid Parameter
Unhandled Exception in EL3.
x30            = 0x000000000401f700
x0             = 0xfffffffffffffffe
x1             = 0xfffffffffffffffe
x2             = 0x00000000600003c0
Signed-off-by: default avatarMing Huang <huangming@linux.alibaba.com>
Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f
      9feb1e2f
    • Jagadeesh Ujja's avatar
      plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF · 4d8c1819
      Jagadeesh Ujja authored 
      

Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF.

Issue :
The Linux prompt hangs when all the cores in a cluster are turned OFF
and we try to turn ON a core in that cluster. Previously when TF-A turns
ON a core, TF-A first turns ON the redistributor followed by the core.
This did not match the flow when turning OFF a core, as TF-A did not
turn OFF redistributor when the corresponding core[s] are disabled.
This hang is resolved by disabling redistributor as cores are disabled,
keeping them in sync.
Signed-off-by: default avatarJagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: Ifd04fdcfd47b45e00f874f15b098471883d023f0
      4d8c1819
    • Rajan Vaja's avatar
      plat: xilinx: versal: Remove code duplication · f621d5fb
      Rajan Vaja authored 
      

Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
      f621d5fb
    • Peng Fan's avatar
      drivers: move scmi-msg out of st · b4734308
      Peng Fan authored 
      

Make the scmi-msg driver reused by others.
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124
      b4734308
  29. 19 Jan, 2021 5 commits