- 15 Jan, 2020 14 commits
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Wendy Liang authored
Enable IPI mailbox service on versal platform. Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Idfba3bcd7e7b868133da0bc1d03c96db2d0bb1b7
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Tejas Patel authored
Add PM IOCTL EEMI. Below PLL related IOCTLs are not available in versal PLM. * IOCTL_SET_PLL_FRAC_MODE * IOCTL_GET_PLL_FRAC_MODE * IOCTL_SET_PLL_FRAC_DATA * IOCTL_SET_PLL_FRAC_DATA PLM has new EEMI APIs for PLL related operations. Call them instead of passing IOCTL API to PLM. For other IOCTL, ATF just pass through IOCTL request to PLM (Platform Loader and Manager). Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I96f8da46a4d3965c9291b7b2da96056408137839
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Tejas Patel authored
Add power down/restart related below API - Force power down - System shutdown Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Icd4a922923b1fd50eca1f5361f1e604aedcdb529
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Tejas Patel authored
Add SMC handler for EEMI API calls coming from EL1/EL2. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: If0ef2a1f2cfc2747be6b91828371bcbec56b1e15
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Tejas Patel authored
Implement below PLL related APIs: - Set PLL parameter - Get PLL parameter - Set PLL mode - Get PLL mode Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I37749d05cdb73641d32da120d319cf36df97c73f
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Tejas Patel authored
Implement below clock related APIs: - Clock enable - Clock disable - Clock get status - Clock set divider - Clock get divider - Clock set parent - Clock get parent Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ibb3606e88ac6796d9d759226908b2c2997c5fea0
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Tejas Patel authored
Implement below pin control related APIs: - Request pin - Release pin - Set pin function - Get pin function - Set pin parameter value - Get pin parameter value Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ib805cc8c936b63206d44bf1f7bebd0f03f7b3c01
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Tejas Patel authored
Implement below reset related APIs: - Reset assert - Get reset status Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Id42c9d3950a0d69125cb0eab79b75e5d22674f14
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Tejas Patel authored
Implement below device related PM APIs: - Request device - Release device - Set requirement - Get device status Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I9d84b9ee1be3ee6c5f27a4d6dc324113fc1acb68
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Tejas Patel authored
Add support for below suspend related APIs. - self_suspend - abort_suspend - request_suspend Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: If568e0cd33b64754fe66f66fc0cdd0ec62c1b32e
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Tejas Patel authored
Add support for EEMI API get_api_verion. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ic1ef90a194ae6164994a7fc5d8ff0b7b192636fe
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Tejas Patel authored
Port ZynqMP PM services for versal to send PM APIs to PMC using IPI. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da
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Tejas Patel authored
Move versal_def.h to platform specific include directory. Also, update source file to include header file from updated path of versal_def.h Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91
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Tejas Patel authored
Move versal_private.h to platform specific include directory. Also, rename it to plat_private.h instead of having platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I65eefbea7722ffa2760b992491c00eebef5bcef4
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 03 Apr, 2019 1 commit
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Ambroise Vincent authored
The default implementations are defined in crash_console_helpers.S. The platforms have to define plat_crash_console_*. Implemented placeholders for platforms that were missing helpers. Change-Id: Iea60b6f851956916e421dfd8c34a62d96eb9148e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 09 Nov, 2018 1 commit
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Siva Durga Prasad Paladugu authored
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. This patch adds Virtual QEMU platform support for this SoC "versal_virt". Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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