- 25 Feb, 2021 1 commit
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Konstantin Porotchkin authored
Map IO WIN to CP1 and CP2 at all stages including the BLE. Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly. This patch allows access to CP1/CP2 internal registers at BLE stage if CP1/CP2 are connected. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com>
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- 30 Jul, 2020 3 commits
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Alex Evraev authored
As the preparation for adding the CN913x SoC family support introduce code that enable SVC and the frequency handling specific for the AP807 North Bridge. Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Grzegorz Jaszczyk authored
Update AVS settings and remove unused macros. This is a preparation patch for adding CN913x SoC family support. Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Alex Evraev authored
Add support for “AVS reduction” feature at this mode for 7040 Dual Cluster operation mode at CPU=1600MHz Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2 Signed-off-by: Alex Evraev <alexev@marvell.com>
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- 06 Jun, 2020 3 commits
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Alex Leibovich authored
Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com>
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Grzegorz Jaszczyk authored
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Dec, 2018 2 commits
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Konstantin Porotchkin authored
Add support for SVC test builds for tuning AVS values. Update the SVC procedure and add EEPROM access. Add support for AP807 AVS values (10 bits wide). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Christine Gharzuzi authored
- Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 03 Sep, 2018 1 commit
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Christine Gharzuzi authored
- add svc configuration according to values burnt to the chip efuse Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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- 02 Sep, 2018 1 commit
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Konstantin Porotchkin authored
Rename a8k_common.h to armada_common.h to keep the same header name across all other Marvell Armada platforms. This is especially useful since various Marvell platforms may use common platform files and share the driver modules. Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 18 Jul, 2018 1 commit
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Konstantin Porotchkin authored
Add common Marvell ARMADA platform components. This patch also includes common components for Marvell ARMADA 8K platforms. Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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